Abstract: A semiconductor device may include a mat array. and a plurality of memory cell mats each including bit lines. The memory cell mats may be included in the mat array. The semiconductor device may include edge sense amplifier blocks comprising edge sense amplifiers coupled to half of the bit lines of the outermost memory cell mats among the memory cell mats. The half of the bit lines of the outermost memory cell mats may be coupled to the edge sense amplifiers, respectively, and may be configured for a first input. The semiconductor device may include half dummy mats each having an area corresponding to half of the area of a memory cell mat of the plurality of memory cell mats and configured to provide reference bit lines for a second input to the edge sense amplifiers, respectively.

Abstract: A semiconductor device may include a mat array, and a plurality of memory cell mats each including bit lines. The memory cell mats may be included in the mat array. The semiconductor device may include edge sense amplifier blocks comprising edge sense amplifiers coupled to half of the bit lines of the outermost memory cell mats among the memory cell mats. The half of the bit lines of the outermost memory cell mats may be coupled to the edge sense amplifiers, respectively, and may be configured for a first input. The semiconductor device may include half dummy mats each having an area corresponding to half of the area of a memory cell mat of the plurality of memory cell mats and configured to provide reference bit lines for a second input to the edge sense amplifiers, respectively.

Abstract: A semiconductor device includes: a Through Silicon Via (TSV) region extending in a first direction and crossing a center portion of a semiconductor device; a plurality of cell regions disposed at both sides of the TSV region in a second direction crossing the first direction; a plurality of peripheral circuit regions each disposed between the TSV region and a corresponding cell region or between two neighboring cell regions in the first direction; a plurality of test pad regions each disposed at an edge portion of the semiconductor device and having a plurality of test pads, wherein the plurality of test pad regions encloses the cell regions, the peripheral circuit regions, and the TSV region; and a reservoir capacitor disposed below corresponding test pads in a test pad regions.

Abstract: A semiconductor device includes: a Through Silicon Via (TSV) region extending in a first direction and crossing a center portion of a semiconductor device; a plurality of cell regions disposed at both sides of the TSV region in a second direction crossing the first direction; a plurality of peripheral circuit regions each disposed between the TSV region and a corresponding cell region or between two neighboring cell regions in the first direction; a plurality of test pad regions each disposed at an edge portion of the semiconductor device and having a plurality of test pads, wherein the plurality of test pad regions encloses the cell regions, the peripheral circuit regions, and the TSV region; and a reservoir capacitor disposed below corresponding test pads in a test pad regions.

Abstract: A delay lock loop circuit for a semiconductor memory element generates a synchronized internal clock signal by receiving an external clock signal as an input. The delay lock loop circuit generates a clock signal having a very fast period in order to enhance speed of data being synchronized by a clock signal. The delay lock loop (DLL) circuit includes: a N frequency dividing means which respectively receives the external signal having the frequency f, and generates a signal having a frequency f/N; a N delay lock loop means which respectively receives the signal having the frequency f/N generated from the N frequency dividing means, and maintains it for a predetermined period; and a merging means which performs a logic operation on each output pulse signal generated from the N delay lock loop means, and generates the synchronised internal signal.

Abstract: A circuit and a method for securing a write recovery operation in a semiconductor memory device. The write recovery security circuit comprises an external signal output unit for outputting an external signal in response to a pulse signal, a external enable signal and a write recovery signal, an external signal latch unit for performing a latch operation in response to the pulse signal, the external enable signal and the write recovery signal to latch an inverted one of the external signal from the external signal output unit while a write recovery operation is performed, and a pulse generator for supplying the pulse signal to the external signal output unit and the external signal latch unit in response to the write recovery signal and transferring the inverted external signal from the external signal output unit to the external signal latch unit in response to the pulse signal.