Abstract: A memory controller may detect degradation in accordance with a bit error rate (BER) of the resistive memory device including memory cells. The memory controller may control the memory cells to be programmed to a first resistance state, read the programmed memory cells, and receive the BER of the memory cells generated during a read operation from the resistive memory device. The memory controller may determine a quantity of program cycles of the memory cells based on the BER. The quantity may be determined based on reference to a lookup table indicating a correlation between the BER and the quantity of program cycles.

Abstract: In some example embodiments, a program pulse is applied to a resistive memory cell and a plurality of post pulses are applied to the resistive memory cell at a time point after a relaxation time from a time point when application of the program pulse is finished, the plurality of post pulses having voltage levels that increase sequentially. Programming speed and/or performance of the resistive memory device may be enhanced by accelerating resistance drift of the resistive memory cell using the plurality of post pulses having the voltage levels that increase sequentially.

Abstract: A memory controller may control a resistive memory device including memory cells may control the resistive memory device to program the memory cells into a first resistance state, control the resistive memory device to read data from the memory cells that are programmed, receive bit error rates (BER) of the memory cells, occurring in a read operation, from the resistive memory device, may determine the number of program operations on the memory cells corresponding to the BER and may, based on the number of program operations that is determined, control the memory cells to be programmed into the first resistance state by using a write current having a current level higher than that of a minimum write current required for the memory cells to be changed into the first resistance state.

Abstract: In some example embodiments, a program pulse is applied to a resistive memory cell and a plurality of post pulses are applied to the resistive memory cell at a time point after a relaxation time from a time point when application of the program pulse is finished, the plurality of post pulses having voltage levels that increase sequentially. Programming speed and/or performance of the resistive memory device may be enhanced by accelerating resistance drift of the resistive memory cell using the plurality of post pulses having the voltage levels that increase sequentially.

Abstract: A memory controller may detect degradation in accordance with a bit error rate (BER) of the resistive memory device including memory cells. The memory controller may control the memory cells to be programmed to a first resistance state, read the programmed memory cells, and receive the BER of the memory cells generated during a read operation from the resistive memory device. The memory controller may determine a quantity of program cycles of the memory cells based on the BER. The quantity may be determined based on reference to a lookup table indicating a correlation between the BER and the quantity of program cycles.

Abstract: A memory controller may control a resistive memory device including memory cells may control the resistive memory device to program the memory cells into a first resistance state, control the resistive memory device to read data from the memory cells that are programmed, receive bit error rates (BER) of the memory cells, occurring in a read operation, from the resistive memory device, may determine the number of program operations on the memory cells corresponding to the BER and may, based on the number of program operations that is determined, control the memory cells to be programmed into the first resistance state by using a write current having a current level higher than that of a minimum write current required for the memory cells to be changed into the first resistance state.