Abstract: In certain embodiments, a method includes the following steps. An engineering change order (ECO) is for fixing a violation of a target constraint on a target netlist of an integrated circuit. A constraint on a related netlist of the integrated circuit is identified. The identified constraint is adversely affected by fixing the violation of the target constraint. A processor concurrently modifies the target netlist to fix the violation of the target constraint and modifies the related netlist to prevent violation of the adversely affected constraint.

Abstract: In certain embodiments, a method includes the following steps. An engineering change order (ECO) is for fixing a violation of a target constraint on a target netlist of an integrated circuit. A constraint on a related netlist of the integrated circuit is identified. The identified constraint is adversely affected by fixing the violation of the target constraint. A processor concurrently modifies the target netlist to fix the violation of the target constraint and modifies the related netlist to prevent violation of the adversely affected constraint.

Abstract: Some embodiments determine a merged timing graph for a multi-instance module (MIM), wherein each node in the merged timing graph corresponds to a pin in the MIM, and wherein each node in the merged timing graph stores timing information associated with the corresponding pins in multiple instances of the MIM in a circuit design. The embodiments can then determine an ECO for the MIM based on the merged timing graph.

Abstract: Some embodiments determine a merged timing graph for a multi-instance module (MIM), wherein each node in the merged timing graph corresponds to a pin in the MIM, and wherein each node in the merged timing graph stores timing information associated with the corresponding pins in multiple instances of the MIM in a circuit design. The embodiments can then determine an ECO for the MIM based on the merged timing graph.

Abstract: A system and a method are disclosed for displaying an output of a static timing analysis. A plurality of timing violations of an integrated circuit is identified. The timing violations are associated with a timing path. A reason is identified for each of the timing violations. A priority for fixing the timing violations is determined. Information describing the timing violations is sent for being presented. The information presented includes an information indicating priority associated with timing violations to assist developers in prioritizing tasks for fixing the timing violations.

Abstract: A system and a method are disclosed for displaying an output of a static timing analysis. A plurality of timing violations of an integrated circuit is identified. The timing violations are associated with a timing path. A reason is identified for each of the timing violations. A priority for fixing the timing violations is determined. Information describing the timing violations is sent for being presented. The information presented includes an information indicating priority associated with timing violations to assist developers in prioritizing tasks for fixing the timing violations.