Abstract: A complex weighting device contains parallel all-pass networks selectively feeding a pair of differential amplifiers, so as to produce a set of mutually orthogonal vector outputs. These outputs are coupled to an attenuator network comprised of dual gate field effect transistors for controllably attenuating the vector outputs of the differential amplifiers. The attenuated vectors are selectively combined to realize a prescribed degree of phase shift from 0.degree. to 360.degree. through the complex weight.

Abstract: An amplitude/phase discriminator network the entirety of which is integrated on the same (GaAs) semiconductor chip, obtains a quadrature phase split through the use of a pair of orthogonal phase generators each of which comprises an all-pass network coupled with a pair of differential amplifiers. An unknown signal of interest, the phase and amplitude of which are to be derived, is applied to one pair of all-pass networks, while a reference signal, the amplitude and phase of which are known, is applied to the other pair of all-pass networks. Four quadrature outputs produced by the differential amplifiers contained within the pair of orthogonal phase generators are selectively coupled to a signal combining stage comprised of a diode detector-low pass filter network.

Abstract: A monolithic FET bridge attenuator contains four single gate FETs, the source-drain path of each of which forms a respective arm of the bridge. The attenuation control electrodes (gates) of the FETs in opposite arms of the bridge are connected to a common control voltage. A first pair of diagonally opposing nodes of the bridge are coupled to receive respective input signals that differ in phase by 180.degree.. A second pair of diagonally opposing nodes of the bridge disposed between the first pair of nodes provide a pair of output signals differing in phase by 180.degree.. In effect, each FET has the electrical behavior of a parallel RC circuit, the resistive component of which is controlled by the gate voltage.

Abstract: A dual gate MESFET attenuator circuit provides substantial range of attenuation without phase shift through a cascaded arrangement of a pair of dual gate MESFETs and the incorporation of a feed forward resistor. By cascading the two transistors together, the attenuation vector characteristics are effectively rotated 180.degree. or shifted to the third and fourth quadrants of the (real/imaginary) vector plane. The resulting phase shift between the minimum attenuation vector and the maximum attenuation vector is compensated by the insertion of a pure resistance component in a feed forward fashion between the input and output terminals of the cascaded dual MESFET pair. The value of the inserted resistor is chosen so as to effectively make both the maximum attenuation vector and the minimum attenuation vector cophasal, thereby providing a constant phase shift through the attenuator over a substantial range of attenuation.