Abstract: A method for configuring/reconfiguring a limited broadcast route within a bridge-connected network. The method includes an algorithm, which configures a minimum spanning tree route. A source node generates and transmits a search frame with indicia set to a value representative of a configuration time. Each bridge in the network receives the frame and determines if the setting of the indicia matches the setting of a time code in said bridge. If there is a match, the bridge discards the frame. Otherwise, the frame is forwarded and the bridge is characterized as a limited broadcast (LB) bridge. The process is repeated at subsequent bridges until a leaf bridge is determined. Thereafter, broadcast messages are permitted to advance through the LB bridges.

Abstract: A plurality of stations are used to strip expendable messages from a serial ring communication network. One station uses either the destination address field or the source address field as the basis for removing a portion of the message. Another station uses the status of a control indicia as the basis for removing the remaining portion of the message from the ring. By distributing the stripping function, between multiple stations on the ring, a significant reduction in ring latency is achieved.

Abstract: Stations on a token ring network use a "Secondary Transmit Opportunity" protocol to transmit information onto the ring. According to the protocol a ring station detecting an idle character immediately following an abort sequence or a physical trailer sequence on the ring may insert a message. Simultaneously, the ring station monitors an input bit stream to detect messages and tokens from upstream stations. If this condition is detected, the station aborts or continues transmission in accordance with a predefined message priority algorithm.

Abstract: A multiprocessor system is described which allows for the sharing of memories between the individual processors having synchronous memory interfaces. Three processing units are shown by way of example, each processor having its own local, associated memory. Two of the processing units can each access its own memory but not any other memory. The third processing unit can access its own memory as well as the memories associated with the other two processing units. An engine interface adapter interconnects the I/O busses of the processing units. The functions performed by the engine interface adapter can be divided into two principal groups. The first group of functions permits communication between the processors via their I/O busses. The second group of functions permits the aforedescribed sharing of the memory units between the processing units.