Abstract: One embodiment of the present invention provides a system that estimates the equivalent capacitances for a set of conductors within an electrical structure. During operation, the system constructs a Gaussian surface that encloses a first conductor, but does not contain any other conductor. The system then computes the equivalent capacitance by constructing a sequence of locations within the electric structure, wherein the first location in the sequence is on the Gaussian surface, and the last location in the sequence is on a second conductor in the set of conductors. Specifically, if a location in the sequence of locations is on the surface of a neighboring conductor that is not in the set of conductors, the system can select the next location in the sequence of locations on a neighboring Gaussian surface that encloses the neighboring conductor, but does not contain any other conductor.

Abstract: One embodiment of the present invention provides a system for estimating parasitic capacitance for an integrated circuit. During operation, the system reads a technology file, which describes the composition of a vertical cross-section of the integrated circuit. Next, the system reads a design file, which specifies the layout of the integrated circuit. The system then identifies a set of dielectric configurations based on information contained in the technology file. It then computes Green's function for each of these configurations. Next, the system estimates a parasitic capacitance using information contained in the design file and using the set of Green's functions.