Abstract: Apparatuses are provided for adjusting the write timing. For instance, the apparatus can include an address/control bus, a write clock data recovery (WCDR) signal bus, and a timing adjustment module. The address/control bus can be configured to concurrently enable a WCDR mode of operation and an active mode of operation. The WCDR signal bus can be configured to transmit WCDR data to a memory device during the WCDR mode of operation. And the timing adjustment module can be configured to adjust a timing based on a phase shift in the WCDR data.

Abstract: A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal.

Abstract: A multi-link input/output (I/O) interface uses both feed-forward and feedback signaling to reduce the impact of noise on data capture at a memory controller. To transfer data from a source module to a destination module, a defined pattern is communicated from the memory module along a master channel concurrent with the memory module providing data via one or more slave channels. Based on the phase of the defined pattern as it is received, the multi-link I/O interface feeds forward to the slave channels control signaling whose phase reflects a predicted noise pattern for the system. Each slave channel performs CDR by adjusting timing of its corresponding capture clock signal based on the fed forward control signaling and based on feedback signaling for the corresponding slave channel, whereby the feedback signaling reflects an error measurement between a phase of a capture clock signal and transitions in received data.

Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on results of an error detection function. For instance, the method can include determining a write timing window between a signal on a data bus and a write clock signal based on the results of the error detection function. The method can also include adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.

Abstract: A multi-link input/output (I/O) interface uses both feed-forward and feedback signaling to reduce the impact of noise on data capture at a memory controller. To transfer data from a source module to a destination module, a defined pattern is communicated from the memory module along a master channel concurrent with the memory module providing data via one or more slave channels. Based on the phase of the defined pattern as it is received, the multi-link I/O interface feeds forward to the slave channels control signaling whose phase reflects a predicted noise pattern for the system. Each slave channel performs CDR by adjusting timing of its corresponding capture clock signal based on the fed forward control signaling and based on feedback signaling for the corresponding slave channel, whereby the feedback signaling reflects an error measurement between a phase of a capture clock signal and transitions in received data.

Abstract: A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal.

Abstract: A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal.

Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on a training signal. For instance, the method can include configuring the memory device in a training mode of operation. The method can also include determining a write timing window between a signal on a data bus and a write clock signal based on the training signal. Further, the method includes adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.

Abstract: Apparatuses are provided for adjusting the write timing. For instance, the apparatus can include an address/control bus, a write clock data recovery (WCDR) signal bus, and a timing adjustment module. The address/control bus can be configured to concurrently enable a WCDR mode of operation and an active mode of operation. The WCDR signal bus can be configured to transmit WCDR data to a memory device during the WCDR mode of operation. And the timing adjustment module can be configured to adjust a timing based on a phase shift in the WCDR data.

Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on a command protocol. For instance, the method can include enabling a write clock data recovery (WCDR) mode of operation. The method can also include transmitting WCDR data from a processing unit to the memory device during the WCDR mode of operation and another mode of operation of the memory device. Based on a phase shift in the WCDR data, a phase difference between a signal on a data bus and a write clock signal can be adjusted. Further, the method can include transmitting the signal on the data bus based on the adjusted phase difference between the signal on the data bus and the write clock signal.

Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on a command protocol. For instance, the method can include enabling a write clock data recovery (WCDR) mode of operation. The method can also include transmitting WCDR data from a processing unit to the memory device during the WCDR mode of operation and another mode of operation of the memory device. Based on a phase shift in the WCDR data, a phase difference between a signal on a data bus and a write clock signal can be adjusted. Further, the method can include transmitting the signal on the data bus based on the adjusted phase difference between the signal on the data bus and the write clock signal.

Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on results of an error detection function. For instance, the method can include determining a write timing window between a signal on a data bus and a write clock signal based on the results of the error detection function. The method can also include adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.

Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on a training signal. For instance, the method can include configuring the memory device in a training mode of operation. The method can also include determining a write timing window between a signal on a data bus and a write clock signal based on the training signal. Further, the method includes adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.

Abstract: A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal.