Abstract: Embodiments of the present invention relate to portions of a switch fabric having a single logical stage and at least one physical stage. In addition, the data paths and the control paths of the switch fabric can be decoupled thereby allowing additional processing to be performed than would otherwise be the case with control rates that matched the high data rates. In other words, data cells received on high speed links can be spread over many lower speed links; consequently, the data cells can transit the switch fabric at that high speed while the control information associated with the data can be processed at that lower speed. Because the control information can be processed at a lower speed (associated with the control path), the control information can be processed over a greater period of time.

Abstract: Embodiments of the present invention relate to portions of a switch fabric having a single logical stage and at least one physical stage. In addition, the data paths and the control paths of the switch fabric can be decoupled thereby allowing additional processing to be performed than would otherwise be the case with control rates that matched the high data rates. In other words, data cells received on high speed links can be spread over many lower speed links; consequently, the data cells can transit the switch fabric at that high speed while the control information associated with the data can be processed at that lower speed. Because the control information can be processed at a lower speed (associated with the control path), the control information can be processed over a greater period of time.

Abstract: Embodiments of the present invention relate to portions of a switch fabric having a single logical stage and at least one physical stage. In addition, the data paths and the control paths of the switch fabric can be decoupled thereby allowing additional processing to be performed than would otherwise be the case with control rates that matched the high data rates. In other words, data cells received on high speed links can be spread over many lower speed links; consequently, the data cells can transit the switch fabric at that high speed while the control information associated with the data can be processed at that lower speed. Because the control information can be processed at a lower speed (associated with the control path), the control information can be processed over a greater period of time.

Abstract: Embodiments of the present invention relate to portions of a switch fabric having a single logical stage and at least one physical stage. In addition, the data paths and the control paths of the switch fabric can be decoupled thereby allowing additional processing to be performed than would otherwise be the case with control rates that matched the high data rates. In other words, data cells received on high speed links can be spread over many lower speed links; consequently, the data cells can transit the switch fabric at that high speed while the control information associated with the data can be processed at that lower speed. Because the control information can be processed at a lower speed (associated with the control path), the control information can be processed over a greater period of time.

Abstract: Accordingly, the present invention provides a method and an apparatus of establishing multiple direct memory access connections between a peripheral and a main memory of a computer system. Each of the multiple direct memory access connection is managed in an improved manner such that one or more of the multiple direct memory access connections are non-real-time connections, but real-time operations may be performed the data carried by the non-real time connections. In another aspect of the present invention, a driver may be implemented on the computer system to facilitate the establishment and maintenance of the multiple direct memory access connections. The present inventions reduce arbitration and system interrupt latencies and reduces the management burden of the direct memory access connections on a central processing unit of the computer system.

Abstract: Accordingly, the present invention provides a method and an apparatus of establishing multiple direct memory access connections between a peripheral and a main memory of a computer system. Each of the multiple direct memory access connection is managed in an improved manner such that one or more of the multiple direct memory access connections are non-real-time connections, but real-time operations may be performed on the data carried by the non-real time connections. In another aspect of the present invention, a driver may be implemented on the computer system to facilitate the establishment and maintenance of the multiple direct memory access connections. The present inventions reduce arbitration and system interrupt latencies and reduces the management burden of the direct memory access connections on a central processing unit of the computer system.