Abstract: An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array includes obtaining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC, adding at least one first-in-first-out (FIFO) buffer to at least one of the communication channels, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.

Abstract: Method, system, and programs for event state management in stream processing. In one example, a batch of events is created from a plurality of input events. The batch is associated with a state and is to be processed in one or more stages. The batch of events is stored in a persistent storage. The state associated with the batch is updated based on results of processing the batch in the one or more stages. The state associated with the batch is retrieved.

Abstract: Method, system, and programs for event state management in stream processing. In one example, a batch of events is created from a plurality of input events. The batch is associated with a state and is to be processed in one or more stages. The batch of events is stored in a persistent storage. The state associated with the batch is updated based on results of processing the batch in the one or more stages. The state associated with the batch is retrieved.

Abstract: An embodiment of the present invention includes a pipeline comprising a plurality of stages and a pipeline timing controller controlling a plurality of predetermined delays, wherein, when one of the predetermined delays has expired, the pipeline timing controller sends a control signal to initiate at least one process within associated ones of the plurality of stages.

Abstract: A method and apparatus is disclosed herein for a bus controller that supports a flexible bus protocol that handles pipelined, variable latency bus transactions while maintaining point-to-point (P2P) FIFO ordering of transactions in a non-blocking manner. In one embodiment, the apparatus includes a bus controller to receive a plurality of bus transactions at a first incoming port from a bus. The bus controller is configured to process the plurality of bus transactions in a pipelined manner, maintaining P2P FIFO ordering of the plurality of bus transactions even when the plurality of bus transactions take a variable number of cycles to complete.

Abstract: A method of designing a pipeline comprises the steps of: accepting a task procedure expressed in a standard programming language, the task procedure including a sequence of computational steps; accepting a performance requirement of the pipeline; and automatically creating a hardware description of the pipeline, the pipeline comprising a plurality of interconnected processor stages, each of the processor stages for performing a respective one of the computational steps, the pipeline having characteristics consistent with the performance requirement of the pipeline.

Abstract: A method for determining validity of a proposed loop iteration schedule comprising the steps of receiving a dependence graph including operations and edges between said operations; receiving a performance specification; receiving an assignment of latencies to operations of said dependence graph; and determining existence of a placement of clock cycle-boundaries in said dependence graph such that all dependence and timing constraints are satisfied for the performance specification.

Abstract: A method for performing a global timing analysis of a proposed digital circuit comprising receiving timing models and the proposed digital circuit; determining at least one mode of circuit operation of the proposed digital circuit; deriving a sub-circuit corresponding to each of at least one mode of circuit operation; performing timing analysis on each of the sub-circuits derived corresponding to each of the modes; and combining the timing analysis results for all of the modes to determine an overall maximum circuit delay.

Abstract: A method of considering circuit timing requirements during the circuit design process, comprising receiving a clock cycle-time constraint; receiving delay characteristics of hardware resources from a macrocell library; receiving an operation, an alternative clock cycle associated with said operation and an alternative hardware resource associated with said operation; and determining validity of the received alternative with respect to timing constraints using a hardware structural representation of the program graph.

Abstract: A technique for synthesizing digital circuit designs by incorporating timing convergence and routability considerations. In one aspect, the invention provides a system and programmatic method for generating a circuit design from a functional specification according to at least one design objective. An intermediate representation of the functional specification is formed. The intermediate representation is analyzed for identifying a physical instantiation that will possibly result in unacceptable interconnect delay or congestion. Functional units are allocated from among a plurality of candidate functional units for performing operations of the intermediate representation. Operations are scheduled to occur at specified times on said selected functional units. An architectural representation of the circuit design is formed according to results of scheduling.

Abstract: A method for the automatic design of processor datapaths operates on an abstract input specification of desired processor operations and their instruction level parallelism and synthesizes a datapath design in machine readable form. A datapath synthesizer automatically designs and synthesizes the processor datapath including the number and types of functional units, the number of read/write ports of the various register files, and the exact connectivity between the register files and the functional units. The heuristics used in the implementation maximize resource sharing and minimize the overall cost in by customizing and sharing functional units and minimizing the number of read/write ports on the register files subject to the specified ILP among operations.

Abstract: A computational unit for use in loop computations. The computational unit includes a function unit, a plurality of phase lines, and a storage register. The computational unit is programmed to initiate one iteration of the loop every II cycles. Each function unit has a result output for outputting one computational result each cycle. There is one phase line corresponding to each of the II cycles. The storage register includes a linear connected array of shift cells having a first shift cell. Each shift cell has an input port, an output port, a shift control port, and an OR gate. Each shift cell receives the value to be stored in the shift cell on the input port, the stored value being stored in response to a control signal on the shift control port. The OR gate has an output connected to the shift enable port and one input for each cycle on which that shift cell is to receive the control signal, that input being connected to the phase line corresponding to that cycle.

Abstract: An embodiment of the present invention includes a pipeline comprising a plurality of stages and a pipeline timing controller controlling a plurality of predetermined delays, wherein, when one of the predetermined delays has expired, the pipeline timing controller sends a control signal to initiate at least one process within associated ones of the plurality of stages.

Abstract: A method of designing a pipeline comprises the steps of: accepting a task procedure expressed in a standard programming language, the task procedure including a sequence of computational steps; accepting a performance requirement of the pipeline; and automatically creating a hardware description of the pipeline, the pipeline comprising a plurality of interconnected processor stages, each of the processor stages for performing a respective one of the computational steps, the pipeline having characteristics consistent with the performance requirement of the pipeline.

Abstract: A method for determining validity of a proposed loop iteration schedule comprising the steps of receiving a dependence graph including operations and edges between said operations; receiving a performance specification; receiving an assignment of latencies to operations of said dependence graph; and determining existence of a placement of clock cycle-boundaries in said dependence graph such that all dependence and timing constraints are satisfied for the performance specification.

Abstract: A method of considering circuit timing requirements during the circuit design process, comprising receiving a clock cycle-time constraint; receiving delay characteristics of hardware resources from a macrocell library; receiving an operation, an alternative clock cycle associated with said operation and an alternative hardware resource associated with said operation; and determining validity of the received alternative with respect to timing constraints using a hardware structural representation of the program graph.

Abstract: A technique for synthesizing digital circuit designs by incorporating timing convergence and routability considerations. In one aspect, the invention provides a system and programmatic method for generating a circuit design from a functional specification according to at least one design objective. An intermediate representation of the functional specification is formed. The intermediate representation is analyzed for identifying a physical instantiation that will possibly result in unacceptable interconnect delay or congestion. Functional units are allocated from among a plurality of candidate functional units for performing operations of the intermediate representation. Operations are scheduled to occur at specified times on said selected functional units. An architectural representation of the circuit design is formed according to results of scheduling.

Abstract: A method for performing a global timing analysis of a proposed digital circuit comprising receiving timing models and the proposed digital circuit; determining at least one mode of circuit operation of the proposed digital circuit; deriving a sub-circuit corresponding to each of at least one mode of circuit operation; performing timing analysis on each of the sub-circuits derived corresponding to each of the modes; and combining the timing analysis results for all of the modes to determine an overall maximum circuit delay.

Abstract: A VLIW processor design system automates the design of programmable and non-programmable VLIW processors. The system takes as input an opcode repertoire, the I/O format of the opcodes, a register file specification, and instruction-level parallelism constraints. With this input specification, the system constructs a datapath, including functional units, register files and their interconnect components from a macrocell database. The system uses the input and the datapath to generate an instruction format design. The instruction format may then be used to construct the processor control path. The abstract input and datapath may be used to extract a machine description suitable to re-target a compiler to the processor. To optimize the processor for a particular application program, the system selects custom instruction templates based on operation issue statistics for the application program generated by the re-targeted compiler.

Abstract: An MDES extractor automatically extracts a machine description (MDES) for re-targeting a compiler from a structural representation of a datapath of an explicitly parallel instruction computing (EPIC) processor. The datapath is a machine readable data structure that specifies the functional unit instances and an interconnect of the functional unit instances to registers. The MDES extractor structurally traverses the interconnect, identifying resource conflicts among the operations in the processor's opcode repertoire. Latencies and internal resources of the opcodes associated with the functional unit instances are obtained from a macrocell library. The MDES extractor then identifies external resource conflicts by preparing reservation tables for the functional units.