Abstract: A peer-to-peer monitoring system and method that enable monitoring of execution of various performance core processes by one or more performance core processors in, for example, an autonomous vehicle system. Each performance core processor is integrated on a single chip or die with a corresponding monitoring core processor that monitors its performance, execution of performance core processes, etc. Each monitoring core processor is communicatively coupled to all other monitoring core processors in the peer-to-peer monitoring systems and monitors those processors. Each monitoring core processor, upon receiving a communication from another monitoring core processor may perform various actions to ensure continuity of operation of the peer-to-peer monitoring system and/or the performance core processors.

Abstract: Provided are methods for forming redundant node configurations in a multi-systems-on-a-chip environment. Each system-on-a-chip can include one or processors and memories independent of other systems-on-a-chip and in communication via a cache coherent fabric. To facilitate rapid and extensible reconfiguration, various systems-on-a-chip from the multi-systems-on-a-chip environment can be configured into a redundant node configuration, with each logical node implemented by one or more of the systems-on-a-chip. Each system-on-a-chip within a logical node can be configured to utilize a shared memory space, such as by transparent mirroring of logical memory addresses. Across nodes, systems-on-a-chip can communicate using a device-to-device protocol such as a non-transparent bridge. My reconfiguration of communication between systems-on-a-chip, the multi-systems-on-a-chip environment can be reconfigured to represent a variety of redundant configurations.

Abstract: In an embodiment, a method comprises: running, with a first core of a first multiprocessor system on chip (MPSoC) of a distributed computing architecture, a first process/thread on input data, the first process/thread pinned to the first core; storing, using a cache coherency fabric, first data in shared memory, the first data generated by the first process/thread; fetching, with a second process/thread pinned to a second core of a second MPSoC of the distributed computing architecture, the first data from the shared memory; and running, with the second core of the second MPSoC, the second process/thread on the first data.

Abstract: Provided are systems and methods for a scalable configurable chip architecture. The system includes a first cluster and a second cluster multi-chip modules, and a data network coupling the first cluster to the second cluster. Each multi-chip module in the first cluster of multi-chip modules comprising a first plurality of chips coupled together by a first interconnect, each chip of the first plurality of chips configured to facilitate processing of at least one function of a first set of functions of an autonomous vehicle (AV). Each multi-chip module in the second cluster of multi-chip modules comprising a second plurality of chips coupled together by a second interconnect, each chip of the second plurality of chips configured to facilitate processing of at least one function of a second set of functions of the AV.

Abstract: Provided are methods for sharing access to resources between SoCs, which can include initializing a boot process for an SoC of a set of SoCs, during the boot process, initializing a compute resource of the SoC, the compute resource comprising at least one of an input/output functionality, a processing unit, or memory, during the boot process, identifying a node configuration for the SoC, the node configuration defining a node, wherein the node configuration indicates that the SoC and at least one additional SoC of the set of SoCs correspond to the node, and, during the boot process, sharing access to the compute resource with the at least one additional SoC of the set of SoCs. Systems and computer program products are also provided.

Abstract: A shared cache is point-to-point connected to a plurality of point-to-point connected processing nodes, wherein the processing nodes may be integrated circuits or multiprocessing systems. In response to a local cache miss, a requesting processing node issues a broadcast for requested data which is observed by the shared cache. If the shared cache has a copy of the requested data, the shared cache forwards the copy of the requested data to the requesting processing node.

Abstract: A device includes a connector having first and second signal pins adapted to, when the connector is being connected to a mating connector of another device, make a first connection using the first signal pin prior to making a second connection using the second signal pin, a first circuit operatively coupled to the first signal pin and configured to identify at least three pre-determined signal patterns receivable from the another device using the first connection, wherein each of the at least three pre-determined signal patterns corresponds to one of at least three pre-determined interface protocols, and a second circuit operatively coupled to the first circuit and the second signal pin, wherein the second circuit is configured, responsive to the first circuit identifying a pre-determined signal pattern of the at least three pre-determined signal patterns, to interface with the another device using at least the second signal pin, wherein to interface with the another device is according to a pre-determined in

Abstract: A device includes a connector having first and second signal pins adapted to, when the connector is being connected to a mating connector of another device, make a first connection using the first signal pin prior to making a second connection using the second signal pin, a first circuit operatively coupled to the first signal pin and configured to identify at least three pre-determined signal patterns receivable from the another device using the first connection, wherein each of the at least three pre-determined signal patterns corresponds to one of at least three pre-determined interface protocols, and a second circuit operatively coupled to the first circuit and the second signal pin, wherein the second circuit is configured, responsive to the first circuit identifying a pre-determined signal pattern of the at least three pre-determined signal patterns, to interface with the another device using at least the second signal pin, wherein to interface with the another device is according to a pre-determined in