Abstract: An improved storage replication scheme removes the bottlenecks in the data replication path and allows for high performance replication, both synchronous and asynchronous. The scheme eliminates storage array controllers from the replication data path and provides an implementation of array based replication which can sustain much higher input/output (I/O) write bandwidth with much lower latency from the application's perspective.

Abstract: Described is a redundant array of inexpensive disks (RAID) scheme that manages the wear of individual drives in a RAID set and significantly reduces the probability of more than two drives wearing out at the same time. In one aspect, describe is a method in which at least one of a first and second of the plurality of at least three low endurance flash based solid state devices perform a predetermined percentage of more writes as compared to at least a third of the plurality of at least three low endurance flash based solid state devices. In another aspect, a rebuild operation is performed using Galois Field Multiplication, with one of an integrated circuit and a field programmable gate array (FPGA) being used in preferred implementations.

Abstract: Described is a write scheduling scheme for a SSD that significantly increases read performance, in certain embodiments by about 50% compared to a conventional standard write scheduling schemes, for mixed read-write workloads while maintaining the write bandwidth.

Abstract: A multi-function peripheral component interconnect (PCI) device is disclosed. The device includes a first configuration data structure associated with a first PCI function, a second configuration data structure associated with a second PCI function and a PCI bridge, coupled the first and second configuration data structures. The PCI bridge processes transactions on behalf of the first and second functions.

Abstract: A watchdog timer including a counter, a watchdog enable mechanism, and a timeout control. The watchdog enable mechanism is set to an enabled state by receiving an enabling input and set to a disabled state only by a power cycle or a hardware reset. The timeout control is coupled to the counter and to the watchdog enable mechanism. The timeout control enables a error signal if the watchdog enable mechanism is enabled and the counter is not updated before completing a count.