Patents by Inventor Shailesh Ratilal Gami

Shailesh Ratilal Gami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for testing the validity of shared data in a multiprocessing system
    Patent number: 6922658
    Abstract: A method for a method for testing the validity of shared data in a multiprocessing system is disclosed. The method comprises receiving at a first central processing unit a list of fetch and store instructions associated with blocks in a shared memory location. The list includes a data value, a central processing unit identifier and a relative order associated with the instructions. In addition, one of the data values associated with one of the instructions was stored by a memory-to-memory, memory-to-register or register-to-memory operation. Further, one of the central processing unit identifiers associated with one of the instructions is an identifier corresponding to one of a plurality of central processing units that have access to the shared memory location including the first central processing unit. A fetch operation is performed at a block in the shared memory location from the first central processing unit.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: July 26, 2005
    Assignee: International Business Machines Corporation
    Inventors: Theodore J. Bohizic, Mark H. Decker, Ali Y. Duale, Shailesh Ratilal Gami, Vincent L. Ip, Dennis W. Wittig
  • Method and system for testing the validity of shared data in a multiprocessing system
    Publication number: 20040199363
    Abstract: A method for a method for testing the validity of shared data in a multiprocessing system is disclosed. The method comprises receiving at a first central processing unit a list of fetch and store instructions associated with blocks in a shared memory location. The list includes a data value, a central processing unit identifier and a relative order associated with the instructions. In addition, one of the data values associated with one of the instructions was stored by a memory-to-memory, memory-to-register or register-to-memory operation. Further, one of the central processing unit identifiers associated with one of the instructions is an identifier corresponding to one of a plurality of central processing units that have access to the shared memory location including the first central processing unit. A fetch operation is performed at a block in the shared memory location from the first central processing unit.
    Type: Application
    Filed: March 31, 2003
    Publication date: October 7, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Theodore J. Bohizic, Mark H. Decker, Ali Y. Duale, Shailesh Ratilal Gami, Vincent L. Ip, Dennis W. Wittig