Abstract: A microprocessor chip has instruction pipeline circuitry, and instruction classification circuitry that classifies instructions as they are executed into a small number of classes and records a classification code value. An on-chip table has entries corresponding to a range of addresses of a memory and designed to hold a statistical assessment of a value of consulting an off-chip table in a memory of the computer. Lookup circuitry is designed to fetch an entry from the on-chip table as part of the basic instruction processing cycle of the microprocessor. A mask has a value set at least in part by a timer. The instruction pipeline circuitry is controlled based on the value of the on-chip table entry corresponding to the address of instructions processed, the current value of the mask, the recorded classification code, and the off-chip table.

Abstract: A system with a single BIST for an IC that includes a number of memory arrays that may have varying latencies, widths, and depths. A serial bus (which may be a debug bus) connects the BIST controller, each of the memory arrays on the IC, and a controller. Each memory array has an associated Design for Test Assist Logic (DAL) block. The DAL associated with any particular memory array recognizes commands from the BIST that are for the associated memory array, controls the execution of write/read commands for the associated array and sends data read from the memory array along with appropriate commands to the comparator after a latency that is appropriate for the associated array Thus, there are standardized commands from the BIST, but each DAL executes these commands in a manner appropriate for the memory array (or arrays) associated with the particular DAL.

Abstract: A computer. When an instruction calling for an architecturally-visible side-effect in an architecturally-visible storage location is recognized, a value is stored representative of an architecturally-visible representation of the side-effect, a format of the representative value being different than an architecturally-visible representation of the side-effect. Execution is resumed without generating the architecturally-visible side-effect. Later, the architecturally-visible representation corresponding to the representative value is written into the architecturally-visible storage location. On a context switch, a context of a first process is written and a context of a second process is loaded to place the second process into execution. At least some instructions maintain results in storage resources outside the context resource set, and instructions are marked to indicate whether or not a context switch may be performed at a boundary of the marked instruction.

Abstract: A system with a single BIST for an IC that includes a number of memory arrays that may have varying latencies, widths, and depths. A serial bus (which may be a debug bus) connects the BIST controller, each of the memory arrays on the IC, and a controller. Each memory array has an associated Design for Test Assist Logic (DAL) block. The DAL associated with any particular memory array recognizes commands from the BIST that are for the associated memory array, controls the execution of write/read commands for the associated array and sends data read from the memory array along with appropriate commands to the comparator after a latency that is appropriate for the associated array Thus, there are standardized commands from the BIST, but each DAL executes these commands in a manner appropriate for the memory array (or arrays) associated with he particular DAL.

Abstract: A method and a computer for performance of the method. While executing a program on a computer, profileable events occurring in the instruction pipeline are detected. The instruction pipeline is directed to record profile information describing the profileable events essentially concurrently with the occurrence of the profileable events. The detecting and recording occur under control of hardware of the computer without software intervention.

Abstract: A computer. An instruction pipeline and memory access unit execute instructions in a logical address space of a memory of the computer. An address translation circuit translates address references generated by the program from the program's logical address space to the computer's physical address space. Profile circuitry is cooperatively interconnected with the instruction pipeline and configured to detect, without compiler assistance for execution profiling, occurrence of profilable events occurring in the instruction pipeline, and is cooperatively interconnected with the memory access unit to record profile information describing physical memory addresses referenced during an execution interval of the program.

Abstract: A computer has a multi-stage execution pipeline and an instruction decoder.

Abstract: A microprocessor chip has instruction pipeline circuitry, and instruction classification circuitry that classifies instructions as they are executed into a small number of classes and records a classification code value. An on-chip table has entries corresponding to a range of addresses of a memory and designed to hold a statistical assessment of a value of consulting an off-chip table in a memory of the computer. Lookup circuitry is designed to fetch an entry from the on-chip table as part of the basic instruction processing cycle of the microprocessor. A mask has a value set at least in part by a timer. The instruction pipeline circuitry is controlled based on the value of the on-chip table entry corresponding to the address of instructions processed, the current value of the mask, the recorded classification code, and the off-chip table.

Abstract: A method and computer for performance of the method. While executing a program on a computer, the computer uses registers of a general register file for storage of instruction results. Profile information describing the profileable events is recorded into the general register file as the profileable events occur, without first capturing the information into a main memory of the computer.

Abstract: A method and apparatus for out-of-order memory processing within an in-order processing device includes processing that allows a plurality of memory transactions to be processed in a pipeline manner until a dependency arises between two or more memory transactions. Such processing includes, for each of the plurality of memory transactions, determining whether data associated with the transaction is stored in local cache. If the data is stored in local cache, it is written into a data register in a next pipeline interval. The processing continues by storing the memory transaction in a miss buffer when the data associated with the memory transaction is not stored in the local cache. The processing continues by writing the associated data for the memory transaction identified in the missed buffer into the data register when the data is received without regard to the pipeline manner.

Abstract: An integrated computing system includes at least one processor formed on a substrate, wherein the processor operates at a processor rate. The integrated computing system further includes a global bus that is coupled to the at least one processor and is formed on the substrate. The global bus supports transactions (e.g., data, operational instructions, and/or control signaling conveyances) at a rate that is equal to or greater than the processing rate. The integrated computing system further includes a device gateway and memory gateway that are operably coupled to the global bus and formed on the substrate. The device gateway provides an interface for at least one device (e.g., internal or external) to the global bus. The memory gateway provides an interface between the global bus and memory.

Abstract: A branch resolution logic for an in-order processor is provided which scans the stages of processor pipeline to determine the oldest branch instruction having sufficient condition codes for resolution. The stages are scanned in order from the latter stages to the earlier stages, which allows quick and simple branch resolution. Therefore, because branches are resolved as soon as the necessary condition codes are generated in a specific stage, branch mispredict penalties are minimized.

Abstract: A method and apparatus for busing data elements within a computing system includes processing that begins by providing, on a shared bus, a first control signal relating to a first transaction during a first bus cycle. The processing continues by providing a second control signal relating to a second transaction and a first address signal relating to the first transaction during a second bus cycle. The processing continues by providing a third control signal relating to a third transaction and a second address signal relating to a second transaction during a third bus cycle. The processing then continues by providing a first status relating to the first transaction and a third addressing signal relating to the third transaction during a fourth bus cycle. The processing then continues by providing a second status relating to the second transaction during a fifth bus cycle.

Abstract: A method and apparatus for interfacing a processor with a bus includes processing that begins by storing transactions initiated by the processor into a buffer. The processing then continues by selecting one of the transactions stored in the buffer and placing the selected transaction on the bus. The processing continues by monitoring progress of fulfillment of each transaction in the buffer and flagging a transaction when it has been successfully completed. The processing also includes processing at least two related transactions prior to selecting one of the transactions from the buffer where, if transactions can be processed locally, they do not need to be transported on the bus. In addition, the processing includes monitoring the bus for related transactions initiated by another processor such that these transactions can be more efficiently processed. The related transaction on the bus would correspond to a transaction queued in the buffer.

Abstract: A method and apparatus for both facilitating access to shared memory addresses over a common bus by a plurality of data processors includes detecting, by at least a first processor, that two access addresses are boundary addresses on either side of an address boundary. The method and apparatus locks the common bus in response to detecting the two access addresses. In addition, the method and apparatus locks the two detected addresses based on address probe inquiry data communicated by the first processor. Accordingly, at least one processor employs probe based bus lock and address lock control to facilitate efficient access to shared memory addresses. Preferably, each processor includes probe-based bus lock and address locking control. The method and apparatus provides a type of address locking with deterministic bus locking when needed.

Abstract: A microprocessor die contains several processor cores and a shared cache. Trigger conditions for one or more of the processor cores are programmed into debug registers. When a trigger is detected, a trace record is generated and loaded into a debug queue on the microprocessor die. Several trace records from different processor cores can be rapidly generated and loaded into the debug queue. The external interface cannot transfer these trace records to an external in-circuit emulator (ICE) at the rate generated. The debug queue transfers trace records to the external ICE using a dedicated bus to the ICE so that bandwidth is not taken from the memory bus. The memory bus is not slowed for debugging, providing a more realistic debugging session. The debug buffer is also used as a video FIFO for buffering pixels for display on a monitor. The dedicated bus is connected to an external DAC rather than to the external ICE when debugging is not being performed.

Abstract: A pipelined processor is modified to efficiently process repeated string instructions. A repeated string instruction repeats an iteration a number of times determined by a counter variable stored in a register file. Each iteration includes at least three pipeline flows to perform a load, store, or compare of a character in the string, and to decrement the counter variable. When the last flow of an iteration reaches the execute stage near the end of the pipeline, the current value of the counter variable is compared to the maximum number of iterations which may be present in the pipeline at one time. When the counter variable is equal to the maximum number of iterations, the execute stage signals the decode stage to stop dispatching iterations. The iterations in the pipeline are completed, providing the proper number of iterations.

Abstract: A superscalar processor can dispatch two instructions per clock cycle. The first instruction is decoded from instruction bytes in a large instruction buffer. A secondary instruction buffer is loaded with a copy of the first few bytes of the second instruction to be dispatched in a cycle. In the previous cycle this secondary instruction buffer is used to determine the length of the second instruction dispatched in that previous cycle. That second instruction's length is then used to extract the first bytes of the third instruction, and its length is also determined. The first bytes of the fourth instruction are then located. When both the first and the second instructions are dispatched, the secondary buffer is loaded with the bytes from the fourth instruction. If only the first instruction is dispatched, then the secondary buffer is loaded with the first bytes of the third instruction. Thus the secondary buffer is always loaded with the starting bytes of undispatched instructions.

Abstract: A mixed-modulo address generation unit has several inputs. The unit effectively adds together a subset of these inputs in a reduced modulus while simultaneously adding other inputs in a full modulus to the partial sum of reduced-modulus inputs. The subset of inputs receives reduced-width address components such as 16-bit address components which are effectively added together in modulo 64K. The other inputs receive full-width address components such as 32-bit components which are added in the full modulus, 4G. Reduced-width components are zero-extended to 32 bits before input to a standard 32-bit adder. A 16-bit carry generator also receives the reduced-width components and generates the carries out of the 16th bit position. When one or more carries is detected, a correction term is subtracted from the initial sum which is recirculated to the adder's input in a subsequent step. The correction term is the number of carries out of the 16th bit position multiplied by 64K.

Abstract: The dispatch unit of a superscalar processor checks for register dependencies among instructions to be issued together as a group. The first instruction's destination register is compared to the following instructions' sources, but the destinations of following instructions are not checked with the first instruction's destination. Instead, instructions with destination-destination dependencies are dispatched together as a group. These instructions flow down the pipelines. At the end of the pipelines the destinations are compared. If the destinations match then the results are merged together and written to the register. When instructions write to only a portion of the register, merging ensures that the correct portions of the register are written by the appropriate instructions in the group. Thus older code which performs partial-register writes can benefit from superscalar processing by dispatching the instructions together as a group and then merging the writes together at the end of the pipelines.