Abstract: Systems and methods for enabling Reliability, Availability & Serviceability features after launching a secure environment under the control of LaGrande Technology (LT), or comparable security technology, without compromising security are provided. In one embodiment, the method comprises adding at least one specific capability to a processor to enable at least one of CPU hot-plug, CPU migration, CPU hot removal and capacity on demand.

Abstract: Multi-node and multi-processor security management is described in this application. Data may be secured in a TPM of any one of a plurality of nodes, each node including one or more processors. The secured data may be protected using hardware hooks to prevent unauthorized access to the secured information. Security hierarchy may be put in place to protect certain memory addresses from access by requiring permission by VMM, OS, ACM or processor hardware. The presence of secured data may be communicated to each of the nodes to ensure that data is protected. Other embodiments are described.

Abstract: Multi-node and multi-processor security management is described in this application. Data may be secured in a TPM of any one of a plurality of nodes, each node including one or more processors. The secured data may be protected using hardware hooks to prevent unauthorized access to the secured information. Security hierarchy may be put in place to protect certain memory addresses from access by requiring permission by VMM, OS, ACM or processor hardware. The presence of secured data may be communicated to each of the nodes to ensure that data is protected. Other embodiments are described.

Abstract: In some embodiments, the integrity of firmware stored in a non-volatile memory is verified prior to initiation of a firmware reset vector. Other embodiments are described and claimed.

Abstract: A method includes determining a plurality of memory addresses, each memory address being different from one another. The method further includes generating a plurality of system management interrupt interprocessor interrupts, each system management interrupt interprocessor interrupt having a corresponding processor in a plurality of processors in a system and each system management interrupt interprocessor interrupt including one of the plurality of memory addresses. The method further includes directing each system management interrupt interprocessor interrupt to the corresponding processor. An associated machine readable medium is also disclosed.

Abstract: Systems and methods for enabling Reliability, Availability & Serviceability features after launching a secure environment under the control of LaGrande Technology (LT), or comparable security technology, without compromising security are provided. In one embodiment, the method comprises adding at least one specific capability to a processor to enable at least one of CPU hot-plug, CPU migration, CPU hot removal and capacity on demand.

Abstract: Embodiments of a system and method for servicing a hidden execution mode event in a multiprocessor computer system is described. A plurality of event handlers and shared memory resources are loaded or stored in a transactional memory space that is accessible to a hidden execution mode supported by each of a plurality of processors in the multiprocessor system. The event handlers are dispatched to different processors among the plurality of processors in response to the hidden execution mode event. A resource locking mechanism comprising a linked-list mechanism that stores entries consisting of work items to be executed by the processors, enables a specified resource of the one or more shared resources to be accessed by only one event handler at a time. The hidden execution mode event comprises a System Management Mode of a microprocessor, and the hidden execution mode event can be either a System Management Interrupt event or a Processor Management Interrupt event.

Abstract: Apparatus and systems, as well as methods and articles, may operate to detect an input/output access operation associated with a configuration memory address and a first memory address bit size. The configuration memory address and associated configuration data may be combined into a packet having a second memory address bit size (e.g., 64 bits) greater than the first memory address bit size (e.g., 32 bits). The packet may be used to establish compatibility for legacy operating systems that attempt to communicate with peripheral component interconnect (PCI) interface-based peripherals, and similar platform devices, that have been integrated into the same package as the processor.

Abstract: Methods and apparatus to reinitiate failed processors in multiple-processor systems are described herein. In an example method, a failure associated with a first processor of a plurality of processors in a multiple-processor system is detected by a second processor of the plurality of processors. In response to detection of the failure associated with the first processor, the second processor restores the first processor.

Abstract: Methods and apparatus to reinitiate failed processors in multiple-processor systems are described herein. In an example method, a failure associated with a first processor of a plurality of processors in a multiple-processor system is detected by a second processor of the plurality of processors. In response to detection of the failure associated with the first processor, the second processor restores the first processor.

Abstract: A mechanism is provided for booting a computer system that is capable of implementing different instruction set architectures, through a network. An embodiment of the invention includes a network controller implemented for a first ISA and a processor capable of implementing programs written in a second ISA as well as programs written in the first ISA. Following preliminary boot operations provided through non-volatile system memory, a network boot program provided by the network controller is implemented. The boot program requests the non-volatile system memory for an indication of the operating system to be loaded and generates a boot request for the indicated operating system. When the indicated operating system is written in the second ISA, the boot program loads the OS to a specified location in system memory and sends the processor into a mode suitable for executing the second ISA.

Abstract: A bootstrap processor selection mechanism for a computer system employs system logic having a memory-mapped sticky, e.g. write-once, register, multiple processors, and a firmware routine through which the processors may store values to and load values from the sticky register. When a reset event is detected, the processors vie for access to the sticky register, using the firmware routine. The first processor that successfully stores its associated processor ID to the sticky register, locks the register against subsequent store operations by the remaining processors. Each processor loads the value stored in the sticky register and compares it with its processor ID to determine whether it is the bootstrap processor.

Abstract: A firmware system comprises a legacy firmware module and a native firmware module written for native and legacy instruction set architectures (ISAs), respectively. A data structure is associated with the legacy firmware module to provide access to one or more legacy routines through a first dispatcher. The native firmware nodule includes a prologue routine. The prolog routine locates the data structure associated with the legacy firmware module and initializes it to provide a link between the first and second firmware modules.

Abstract: A device and method for transferring data, address and status information concerning a former I/O bus cycle before a system management interrupt is initiated. A plurality of system management shadow registers samples information from a system bus. Such information is obtained by a register accessing the plurality of system management shadow registers through a common shadow port.