Patents by Inventor Shan Shi

Shan Shi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150287988
    Abstract: The present invitation discloses a high capacity rechargeable battery, which comprises a carbon/manganese dioxide composite cathode; a zinc anode separated from cathode; an aqueous electrolyte contains zinc (Zn2+) and manganese (Mn2+) ions. The present invitation utilizes the oxidation/reduction of Mn2+ ions on carbon/manganese dioxide composite to improve the capacity and the cycle life of the battery.
    Type: Application
    Filed: July 2, 2014
    Publication date: October 8, 2015
    Inventors: Chengjun XU, Yanyi CHEN, Shan SHI, Feiyu KANG
  • Publication number: 20150255792
    Abstract: The present invention discloses a rechargeable zinc ion battery, in which anodic zinc will be electrochemically dissolved as Zn2+ ions, diffuses to the cathodic electrode/electrolyte interface through the electrolyte, and zinc ions subsequently inserted in carbon material during discharging. In charging, above-mentioned process will be reverse. The rechargeable zinc ion battery comprises a carbon cathode; a zinc anode separated from cathode; an aqueous electrolyte contains zinc ions.
    Type: Application
    Filed: July 15, 2014
    Publication date: September 10, 2015
    Inventors: Chengjun XU, Yanyi CHEN, Shan SHI, Feiyu KANG
  • Patent number: 9034713
    Abstract: The present invention provides a method of fabricating a HV MOS transistor device, including forming a deep well in a substrate, and the deep well; forming a first doped region in the deep well, and the first doped region, wherein a doping concentration of the first doped region and a doping concentration of the deep well in at least one electric field concentration region has a first ratio, the doping concentration of the first doped region and the doping concentration of the deep well outside the electric field concentration region has a second ratio, and the first ratio is greater than the second ratio; and forming a high voltage well in the substrate, and forming a second doped region and a third doped region respectively in the deep well and in the high voltage well.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: May 19, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Chung Wang, Wei-Lun Hsu, Shan-Shi Huang, Ke-Feng Lin, Te-Yuan Wu
  • Publication number: 20150079754
    Abstract: The present invention provides a method of fabricating a HV MOS transistor device, including forming a deep well in a substrate, and the deep well; forming a first doped region in the deep well, and the first doped region, wherein a doping concentration of the first doped region and a doping concentration of the deep well in at least one electric field concentration region has a first ratio, the doping concentration of the first doped region and the doping concentration of the deep well outside the electric field concentration region has a second ratio, and the first ratio is greater than the second ratio; and forming a high voltage well in the substrate, and forming a second doped region and a third doped region respectively in the deep well and in the high voltage well.
    Type: Application
    Filed: November 19, 2014
    Publication date: March 19, 2015
    Inventors: Chih-Chung Wang, Wei-Lun Hsu, Shan-Shi Huang, Ke-Feng Lin, Te-Yuan Wu
  • Patent number: 8921937
    Abstract: The present invention provides a high voltage metal-oxide-semiconductor transistor device including a substrate, a deep well, and a doped region. The substrate and the doped region have a first conductive type, and the substrate has at least one electric field concentration region. The deep well has a second conductive type different from the first conductive type. The deep well is disposed in the substrate, and the doped region is disposed in the deep well. The doping concentrations of the doped region and the deep well in the electric field have a first ratio, and the doping concentrations of the doped region and the deep well outside the electric field have a second ratio. The first ratio is greater than the second ratio.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: December 30, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Chung Wang, Wei-Lun Hsu, Shan-Shi Huang, Ke-Feng Lin, Te-Yuan Wu
  • Patent number: 8698247
    Abstract: The present invention provides a semiconductor device including a substrate, a deep well, a high-voltage well, and a doped region. The substrate and the high-voltage well have a first conductive type, and the deep well and the doped region have a second conductive type different from the first conductive type. The substrate has a high-voltage region and a low-voltage region, and the deep well is disposed in the substrate in the high-voltage region. The high-voltage well is disposed in the substrate between the high-voltage region and the low-voltage region, and the doped region is disposed in the high-voltage well. The doped region and the high-voltage well are electrically connected to a ground.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: April 15, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Chung Wang, Wei-Lun Hsu, Te-Yuan Wu, Wen-Fang Lee, Ke-Feng Lin, Shan-Shi Huang, Ming-Tsung Lee
  • Publication number: 20130187225
    Abstract: A HV MOSFET device includes a substrate, a deep well region, a source/body region, a drain region, a gate structure, and a first doped region. The deep well region includes a boundary site and a middle site. The source/body region is formed in the deep well region and defines a channel region. The first doped region is formed in the deep well region and disposed under the gate structure, and having the first conductivity type. There is a first ratio between a dopant dose of the first doped region and a dopant dose of the boundary site of the deep well region. There is a second ratio between a dopant dose of the first doped region and a dopant dose of the middle site of the deep well region. A percentage difference between the first ratio and the second ratio is smaller than or equal to 5%.
    Type: Application
    Filed: January 20, 2012
    Publication date: July 25, 2013
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Chih-Chung WANG, Ming-Tsung Lee, Chung-I Huang, Shan-Shi Huang, Wen-Fang Lee, Te-Yuan Wu
  • Patent number: 8492835
    Abstract: A HV MOSFET device includes a substrate, a deep well region, a source/body region, a drain region, a gate structure, and a first doped region. The deep well region includes a boundary site and a middle site. The source/body region is formed in the deep well region and defines a channel region. The first doped region is formed in the deep well region and disposed under the gate structure, and having the first conductivity type. There is a first ratio between a dopant dose of the first doped region and a dopant dose of the boundary site of the deep well region. There is a second ratio between a dopant dose of the first doped region and a dopant dose of the middle site of the deep well region. A percentage difference between the first ratio and the second ratio is smaller than or equal to 5%.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: July 23, 2013
    Assignee: United Microelectronics Corporation
    Inventors: Chih-Chung Wang, Ming-Tsung Lee, Chung-I Huang, Shan-Shi Huang, Wen-Fang Lee, Te-Yuan Wu
  • Patent number: 8436418
    Abstract: The present invention provides a high-voltage semiconductor device including a deep well, a first doped region disposed in the deep well, a high-voltage well, a second doped region disposed in the high-voltage well, a first gate structure disposed on the high-voltage well between the second doped region and the first doped region, a doped channel region disposed in the high-voltage region and in contact with the second doped region and the deep well, and a third doped region disposed in the high-voltage well. The high-voltage well has a first conductive type, and the deep well, the first doped region, the second doped region, the doped channel region, and the third doped region have a second conductive type different from the first conductive type.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: May 7, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Chung Wang, Wei-Lun Hsu, Te-Yuan Wu, Ke-Feng Lin, Shan-Shi Huang, Ming-Tsung Lee, Wen-Fang Lee
  • Publication number: 20130049114
    Abstract: The present invention provides a high voltage metal-oxide-semiconductor transistor device including a substrate, a deep well, and a doped region. The substrate and the doped region have a first conductive type, and the substrate has at least one electric field concentration region. The deep well has a second conductive type different from the first conductive type. The deep well is disposed in the substrate, and the doped region is disposed in the deep well. The doping concentrations of the doped region and the deep well in the electric field have a first ratio, and the doping concentrations of the doped region and the deep well outside the electric field have a second ratio. The first ratio is greater than the second ratio.
    Type: Application
    Filed: August 24, 2011
    Publication date: February 28, 2013
    Inventors: Chih-Chung Wang, Wei-Lun Hsu, Shan-Shi Huang, Ke-Feng Lin, Te-Yuan Wu
  • Publication number: 20120319189
    Abstract: The present invention provides a high-voltage semiconductor device including a deep well, a first doped region disposed in the deep well, a high-voltage well, a second doped region disposed in the high-voltage well, a first gate structure disposed on the high-voltage well between the second doped region and the first doped region, a doped channel region disposed in the high-voltage region and in contact with the second doped region and the deep well, and a third doped region disposed in the high-voltage well. The high-voltage well has a first conductive type, and the deep well, the first doped region, the second doped region, the doped channel region, and the third doped region have a second conductive type different from the first conductive type.
    Type: Application
    Filed: June 20, 2011
    Publication date: December 20, 2012
    Inventors: Chih-Chung Wang, Wei-Lun Hsu, Te-Yuan Wu, Ke-Feng Lin, Shan-Shi Huang, Ming-Tsung Lee, Wen-Fang Lee
  • Publication number: 20120313175
    Abstract: The present invention provides a semiconductor device including a substrate, a deep well, a high-voltage well, and a doped region. The substrate and the high-voltage well have a first conductive type, and the deep well and the doped region have a second conductive type different from the first conductive type. The substrate has a high-voltage region and a low-voltage region, and the deep well is disposed in the substrate in the high-voltage region. The high-voltage well is disposed in the substrate between the high-voltage region and the low-voltage region, and the doped region is disposed in the high-voltage well. The doped region and the high-voltage well are electrically connected to a ground.
    Type: Application
    Filed: June 9, 2011
    Publication date: December 13, 2012
    Inventors: Chih-Chung Wang, Wei-Lun Hsu, Te-Yuan Wu, Wen-Fang Lee, Ke-Feng Lin, Shan-Shi Huang, Ming-Tsung Lee
  • Publication number: 20080038771
    Abstract: Methods for identifying Quantifiable Internal Reference Standards (QIRS) for immunohistochemistry (IHC). Also disclosed are methods for using QIRS to quantify test antigens in IHC.
    Type: Application
    Filed: June 29, 2007
    Publication date: February 14, 2008
    Applicant: UNIVERSITY OF SOUTHERN CALIFORNIA
    Inventors: Clive Taylor, Shan Shi