Patents by Inventor Shane Hollmer
Shane Hollmer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11107535Abstract: A selection circuit includes: a first selection device coupled between a write IO line and a first node; a second selection device coupled between a read IO line and a second node; a third selection device controllable by a first address decode signal, and coupled between a first bit line and a third node; a fourth selection device controllable by a second address decode signal, and coupled between a second bit line and the third node; a first suppression device controllable by a write enable signal, and coupled between the second node and ground; a second suppression device controllable by a read enable signal, and coupled between the first node and ground; a first isolation device controllable by the write enable signal, and coupled between the first and third nodes; and a second isolation device controllable by the read enable signal, and coupled between the second and third nodes.Type: GrantFiled: September 10, 2019Date of Patent: August 31, 2021Assignee: Adesto Technologies CorporationInventors: John Dinh, Shane Hollmer
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Patent number: 11094375Abstract: A method of controlling a memory device can include: receiving, by an interface, a write command from a host; beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of memory cells arranged in a plurality of array planes; receiving, by the interface, a read command from the host; reconfiguring the write operation in response to detection of the read command during execution of the write operation; beginning execution of a read operation on a second array plane in response to the read command; and restoring the configuration of the write operation after the read operation has at least partially been executed.Type: GrantFiled: March 3, 2020Date of Patent: August 17, 2021Assignee: Adesto Technologies CorporationInventors: Gideon Intrater, Bard Pedersen, Shane Hollmer, Derric Lewis, Stephen Trinh
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Publication number: 20210074365Abstract: A selection circuit includes: a first selection device coupled between a write IO line and a first node; a second selection device coupled between a read IO line and a second node; a third selection device controllable by a first address decode signal, and coupled between a first bit line and a third node; a fourth selection device controllable by a second address decode signal, and coupled between a second bit line and the third node; a first suppression device controllable by a write enable signal, and coupled between the second node and ground; a second suppression device controllable by a read enable signal, and coupled between the first node and ground; a first isolation device controllable by the write enable signal, and coupled between the first and third nodes; and a second isolation device controllable by the read enable signal, and coupled between the second and third nodes.Type: ApplicationFiled: September 10, 2019Publication date: March 11, 2021Inventors: John Dinh, Shane Hollmer
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Publication number: 20200202924Abstract: A method of controlling a memory device can include: receiving, by an interface, a write command from a host; beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of memory cells arranged in a plurality of array planes; receiving, by the interface, a read command from the host; reconfiguring the write operation in response to detection of the read command during execution of the write operation; beginning execution of a read operation on a second array plane in response to the read command; and restoring the configuration of the write operation after the read operation has at least partially been executed.Type: ApplicationFiled: March 3, 2020Publication date: June 25, 2020Inventors: Gideon Intrater, Bard Pedersen, Shane Hollmer, Derric Lewis, Stephen Trinh
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Patent number: 10636480Abstract: A method of controlling a memory device can include: receiving, by an interface, a write command from a host; beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of memory cells arranged in a plurality of array planes; receiving, by the interface, a read command from the host; reconfiguring the write operation in response to detection of the read command during execution of the write operation; beginning execution of a read operation on a second array plane in response to the read command; and restoring the configuration of the write operation after the read operation has at least partially been executed.Type: GrantFiled: May 2, 2016Date of Patent: April 28, 2020Assignee: Adesto Technologies CorporationInventors: Gideon Intrater, Bard Pedersen, Shane Hollmer, Derric Lewis, Stephen Trinh
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Publication number: 20180166130Abstract: A method of controlling a memory device can include: receiving, by an interface, a write command from a host; beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of memory cells arranged in a plurality of array planes; receiving, by the interface, a read command from the host; reconfiguring the write operation in response to detection of the read command during execution of the write operation; beginning execution of a read operation on a second array plane in response to the read command; and restoring the configuration of the write operation after the read operation has at least partially been executed.Type: ApplicationFiled: May 2, 2016Publication date: June 14, 2018Applicant: Adesto technologies CorporationInventors: Gideon Intrater, Bard Pedersen, Shane Hollmer, Derric Lewis, Stephen Trinh
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Patent number: 9812200Abstract: A method of controlling an NVM device can include: (i) receiving, by an interface, a write command from a host; (ii) beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of NVM cells arranged in a plurality of array planes; (iii) receiving, by the interface, a read command from the host; (iv) suspending the write operation in response to detection of the read command during execution of the write operation; (v) beginning execution of a read operation on a second array plane in response to the read command; and (vi) resuming the write operation after the read operation has at least partially been executed.Type: GrantFiled: May 22, 2015Date of Patent: November 7, 2017Assignee: Adesto Technologies CorporationInventors: Gideon Intrater, Bard Pedersen, Shane Hollmer, Derric Lewis, Stephen Trinh
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Patent number: 9368206Abstract: In one embodiment, a capacitive circuit can include: (i) a resistive storage element having a solid electrolyte, a first electrode coupled to a first side of the solid electrolyte, and a second electrode coupled to a second side of the solid electrolyte; (ii) the resistive storage element being configured to be programmed to a low resistance state by application of a program voltage in a forward bias direction to form a conductive path between the first and second electrodes, and being configured to be erased to a high resistance state by application of an erase voltage in a reverse bias direction to substantially dissolve the conductive path; and (iii) a first capacitor having the first electrode coupled to a first side of a first oxide layer, and a third electrode coupled to a second side of the first oxide layer.Type: GrantFiled: July 7, 2014Date of Patent: June 14, 2016Assignee: Adesto Technologies CorporationInventors: John Dinh, Ming Sang Kwan, Venkatesh P. Gopinath, Derric Lewis, Shane Hollmer, John R. Jameson, Michael Van Buskirk
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Publication number: 20160012891Abstract: A method of controlling an NVM device can include: (i) receiving, by an interface, a write command from a host; (ii) beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of NVM cells arranged in a plurality of array planes; (iii) receiving, by the interface, a read command from the host; (iv) suspending the write operation in response to detection of the read command during execution of the write operation; (v) beginning execution of a read operation on a second array plane in response to the read command; and (vi) resuming the write operation after the read operation has at least partially been executed.Type: ApplicationFiled: May 22, 2015Publication date: January 14, 2016Inventors: Gideon Intrater, Bard Pedersen, Shane Hollmer, Derric Lewis, Stephen Trinh
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Patent number: 9208876Abstract: Structures and methods for controlling operation of a programmable impedance element are disclosed herein. In one embodiment, a method of programming/erasing the programmable impedance element can include: (i) receiving a program/erase command to be executed on the programmable impedance element; (ii) generating, in response to the program/erase command, a program/erase pulse for performing a program/erase operation on the programmable impedance element; (iii) generating a time delay from the program/erase pulse, where the time delay includes additional delay to allow for at least partial dissipation of one or more effects caused by the program/erase operation; and (iv) performing, after the time delay has elapsed, a verify operation to determine if the program/erase operation has successfully programmed/erased the programmable impedance element.Type: GrantFiled: March 20, 2015Date of Patent: December 8, 2015Assignee: Adesto Technologies CorporationInventors: Chuanding Cheng, Shane Hollmer
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Patent number: 9047948Abstract: Structures and methods for control of an operating window of a programmable impedance element are disclosed herein. In one embodiment, a semiconductor memory device can include: (i) a memory array having a programmable impedance element; (ii) a register configured to be programmed with data that represents an erase verify value, a program verify value, and a read trip point resistance value, for the memory array; (iii) a controller configured to determine a mode of operation for the memory array; (iv) a register access circuit configured to read the register to obtain data that corresponds to the mode of operation; and (v) a voltage generator configured to generate a reference voltage based on the register data, where the reference voltage is used to perform an operation on the programmable impedance element corresponding to the mode of operation.Type: GrantFiled: July 13, 2012Date of Patent: June 2, 2015Assignee: Adesto Technologies CorporationInventors: John Dinh, Nad Edward Gilbert, Shane Hollmer, Derric Lewis, John Ross Jameson, Daniel C. Wang, Juan Pablo Saenz Echeverry
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Patent number: 9019745Abstract: Structures and methods for controlling operation of a programmable impedance element are disclosed herein. In one embodiment, a method of programming/erasing the programmable impedance element can include: (i) receiving a program/erase command to be executed on the programmable impedance element; (ii) generating, in response to the program/erase command, a program/erase pulse for performing a program/erase operation on the programmable impedance element; (iii) generating a time delay from the program/erase pulse, where the time delay includes additional delay to allow for at least partial dissipation of one or more effects caused by the program/erase operation; and (iv) performing, after the time delay has elapsed, a verify operation to determine if the program/erase operation has successfully programmed/erased the programmable impedance element.Type: GrantFiled: January 17, 2013Date of Patent: April 28, 2015Assignee: Adesto Technology CorporationInventors: Chuanding Cheng, Shane Hollmer
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Patent number: 8659954Abstract: Structures and methods for controlling operation of a programmable impedance element are disclosed herein. In one embodiment, a method of controlling a programmable impedance element can include: (i) receiving a program or erase command to be executed on the programmable impedance element; (ii) selecting an operation algorithm for executing the command, where the operation algorithm is selected from among a plurality of operation algorithms by decoding at least two bits stored in a register; (iii) determining, using the register, a plurality of option variables for the selected operation algorithm, where the option variables are used to set conditions for one or more of a plurality of program and erase operations of the selected operation algorithm; and (iv) executing the command on the programmable impedance element by performing the one or more of the plurality of program and erase operations of the selected operation algorithm.Type: GrantFiled: July 13, 2012Date of Patent: February 25, 2014Assignee: Adesto Technologies CorporationInventors: Derric Lewis, Shane Hollmer, Vasudevan Gopalakrishnan, John Dinh, Foroozan Sarah Koushan, Juan Pablo Saenz Echeverry
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Patent number: 8049551Abstract: A ramp-up circuit for switched capacitor circuits with negative feedback to control the slew rate of in-rush current. Other embodiments are described and claimed.Type: GrantFiled: June 17, 2008Date of Patent: November 1, 2011Assignee: Monolithic Power Systems, Inc.Inventors: Jeff Kotowski, Shane Hollmer
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Publication number: 20090309633Abstract: A ramp-up circuit for switched capacitor circuits with negative feedback to control the slew rate of in-rush current. Other embodiments are described and claimed.Type: ApplicationFiled: June 17, 2008Publication date: December 17, 2009Applicant: MONOLITHIC POWER SYSTEMSInventors: Jeff Kotowski, Shane Hollmer
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Publication number: 20090140774Abstract: A system and method are provided for communicating data among chained circuits. In operation, a period of a signal communicated between a chain of circuits is identified. Additionally, a state of the signal is determined, based on the period of the signal.Type: ApplicationFiled: December 3, 2007Publication date: June 4, 2009Inventors: Jeff Kotowski, Shane Hollmer
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Patent number: 7155357Abstract: An unused state detection circuit is disclosed that detects an unused state in a semiconductor circuit. A semiconductor circuit is “unused” when the unused state detection circuit has not been permanently cleared. When a semiconductor circuit is first powered up, the unused state detection circuit will detect that the semiconductor circuit has not previously been “used” and can automatically activate a boot up procedure or a testing procedure (or both). After the semiconductor circuit is used, the unused state detection circuit provides an indication that the semiconductor circuit is no longer unused. The unused state detection circuit uses the state of a dedicated non-volatile memory array or a dedicated region of the general non-volatile memory portion of the semiconductor circuit to detect whether the semiconductor circuit has been previously unused.Type: GrantFiled: January 9, 2003Date of Patent: December 26, 2006Assignee: Silicon Storage Technology, Inc.Inventor: Shane Hollmer
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Publication number: 20060218425Abstract: An integrated circuit device has a processing unit, a memory management unit, and a memory. The memory management unit is interposed between the memory and the processing unit for controlling access to the memory by the processing unit in one of three modes. In a first mode, called the system mode, the processing unit can access a system program stored in the memory for controlling the resources of the integrated circuit device. In a second mode, called the kernel mode, the processing unit can access an operating system program stored in the memory for controlling the of the integrated circuit device, limited by the system program. Finally in a third mode, called the user mode, the processing unit can access an application program stored in the memory for controlling the resources of the integrated circuit device, limited by the operating system program.Type: ApplicationFiled: January 31, 2006Publication date: September 28, 2006Inventors: Zhimin Ding, Shane Hollmer, Philip Barnett
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Publication number: 20040138841Abstract: An unused state detection circuit is disclosed that detects an unused state in a semiconductor circuit. A semiconductor circuit is “unused” when the unused state detection circuit has not been permanently cleared. When a semiconductor circuit is first powered up, the unused state detection circuit will detect that the semiconductor circuit has not previously been “used” and can automatically activate a boot up procedure or a testing procedure (or both). After the semiconductor circuit is used, the unused state detection circuit provides an indication that the semiconductor circuit is no longer unused. The unused state detection circuit uses the state of a dedicated non-volatile memory array or a dedicated region of the general non-volatile memory portion of the semiconductor circuit to detect whether the semiconductor circuit has been previously unused.Type: ApplicationFiled: January 9, 2003Publication date: July 15, 2004Inventor: Shane Hollmer
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Patent number: 6622230Abstract: A method is provided for selecting a group of memory blocks in a flash memory device given their starting and ending addresses. The method compares the two addresses to determine the multi-block first bit location which is the most significant bit location where the starting and ending addresses have different bits. The method then generates a converted memory block address where bits more significant than the multi-block first bit location are the ending address bits and where bits less significant than, or equal in significance to, the multi-block first bit location are equal to a logic 1. The method also generates a converted complementary memory block address identical to the other converted address except that bits in the bit locations more significant than the multi-block first bit location are the complements of the ending address bits.Type: GrantFiled: November 28, 2000Date of Patent: September 16, 2003Assignees: Advanced Micro Devices, Inc., Fujitsu LimitedInventors: Masaru Yano, Shane Hollmer, Michael Chung