Abstract: In a p-type flash memory array, separate programming and read bit lines are provided. The programming bit line is used only to program the floating gate transistors in the memory cells connected to that bit line. The read bit line is used only to read the state of a floating gate transistor in a selected memory cell connected to that bit line during the operation of the memory circuit. The resulting structure allows the use of low voltages during both programming and operation of the memory array. This makes possible the use of transistors in the memory array with feature sizes less than, for example, 0.18 microns. At the same time variable, unpredictable capacitances associated with each bit line in prior art p-type flash memory structures using comparable low programming voltages are eliminated when a particular memory cell attached to that bit line is being read out.

Abstract: In a p-type flash memory array, separate programming and read bit lines are provided. The programming bit line is used only to program the floating gate transistors in the memory cells connected to that bit line. The read bit line is used only to read the state of a floating gate transistor in a selected memory cell connected to that bit line during the operation of the memory circuit. The resulting structure allows the use of low voltages during both programming and operation of the memory array. This makes possible the use of transistors in the memory array with feature sizes less than, for example, 0.18 microns. At the same time variable, unpredictable capacitances associated with each bit line in prior art p-type flash memory structures using comparable low programming voltages are eliminated when a particular memory cell attached to that bit line is being read out.

Abstract: A single-poly two-transistor PMOS memory cell for multiple-time programming applications includes a PMOS floating gate transistor sharing a drain/source P+ diffusion region with a PMOS select gate transistor all formed within a first n-well. A control plate for the floating gate transistor is formed in a second n-well. A single-poly two-transitor PMOS memory cell for one-time programming applications includes a PMOS floating gate transistor having a source formed as a p+ diffusion region in a single n-well. The source is adapted to also serve as control plate for the floating gate transistor.

Abstract: A single-poly two-transistor PMOS memory cell for multiple-time programming applications includes a PMOS floating gate transistor sharing a drain/source P+ diffusion region with a PMOS select gate transistor all formed within a first n-well. A control plate for the floating gate transistor is formed in a second n-well. A single-poly two-transitor PMOS memory cell for one-time programming applications includes a PMOS floating gate transistor having a source formed as a p+ diffusion region in a single n-well. The source is adapted to also serve as control plate for the floating gate transistor.

Abstract: A two-transistor PMOS memory cell includes a PMOS floating gate transistor sharing a drain/source P+ diffusion region with a PMOS select gate transistor. The shared drain/source diffusion region acts as a drain for the floating gate transistor and as a source to the select gate transistor. The shared drain/source P+ diffusion region is formed in an N? well. Underlying the drain/source P+ diffusion region is a N implant having the same lateral extent of the drain/source P+ diffusion region to provide a lower programming voltage for the floating gate transistor and improved punch-through resistance for the select gate transistor.

Abstract: A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.

Abstract: A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.

Abstract: A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.

Abstract: A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.

Abstract: A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.