Patents by Inventor Shang-Ju TU
Shang-Ju TU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230352574Abstract: A semiconductor component is provided in the form of an enhancement mode high-electron-mobility transistor having an n-i-p semiconductor junction epitaxial structure. The semiconductor component includes: a channel layer and a barrier layer formed on the channel layer. A two-dimensional electron gas (2DEG) is formed in the channel layer adjacent to an interface between the channel layer and the barrier layer. A gate electrode is disposed on the barrier layer. A semiconductor junction structure is disposed and sandwiched between the gate electrode and the barrier layer. The semiconductor junction structure includes a first region doped with a first dopant and in direct contact with the gate electrode, a second region doped with a second dopant different from the first dopant, and a third region being unintentionally doped and sandwiched between the first region and the second region. The semiconductor junction structure depletes a portion of the 2DEG thereunder.Type: ApplicationFiled: April 29, 2022Publication date: November 2, 2023Inventors: Shang-Ju Tu, Tien Ching Feng, Chia-Cheng Liu, Ming-Chin Chen, Yu-Jen Liu, Chung-Chih Tsai, Tsung-Cheng Chang, Ya-Yu Yang
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Publication number: 20210359123Abstract: A semiconductor power device includes a substrate; a buffer structure formed on the substrate; a barrier structure formed on the buffer structure; a channel layer formed on the barrier structure; and a barrier layer formed on the channel layer; wherein the barrier structure includes a first functional layer on the buffer structure, a second functional layer formed between the first functional layer and the buffer structure, a first back-barrier layer on the first functional layer, and an interlayer between the first back-barrier layer and the first functional layer; wherein a material of the first back-barrier layer includes Alx1Ga1-x1N, a material of the first functional layer includes Alx2Ga1-x2N, a material of the interlayer includes Alx3Ga1-x3N, a material of the second functional layer includes Alx4Ga1-x4N, wherein 0<x1?1, 0?x2?1, 0?x3?1, 0?x4<1, and x1?x2; and wherein the first functional layer includes a first thickness, the second functional layer includes a second thickness, and the second thicType: ApplicationFiled: July 28, 2021Publication date: November 18, 2021Inventors: Ya-Yu YANG, Shang-Ju TU, Tsung-Cheng CHANG, Chia-Cheng LIU
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Patent number: 11094814Abstract: A semiconductor power device includes a substrate, a buffer structure formed on the substrate, a barrier structure formed on the buffer structure, a channel layer formed on the barrier structure, and a barrier layer formed on the channel layer. The barrier structure includes a first functional layer on the buffer structure, a first back-barrier layer on the first functional layer, and an interlayer between the first back-barrier layer and the first functional layer. A material of the first back-barrier layer comprises Alx1Ga1-x1N, a material of the first functional layer comprises Alx2Ga1-x2N, 0<x1?1, 0?x2?1, and x1?x2. The interlayer includes a carbon doped or an iron doped material.Type: GrantFiled: September 29, 2017Date of Patent: August 17, 2021Assignee: EPISTAR CORPORATIONInventors: Ya-Yu Yang, Shang-Ju Tu, Tsung-Cheng Chang, Chia-Cheng Liu
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Patent number: 11049961Abstract: A high electron mobility transistor, includes a substrate; a channel layer formed on the substrate; a barrier layer formed on the channel layer; a source electrode and a drain electrode formed on the barrier layer; a depletion layer formed on the barrier layer and between the source electrode and the drain electrode, wherein a material of the depletion layer comprises boron nitride or zinc oxide; and a gate electrode formed on the depletion layer.Type: GrantFiled: June 26, 2019Date of Patent: June 29, 2021Assignee: EPISTAR CORPORATIONInventors: Shang-Ju Tu, Chia-Cheng Liu, Tsung-Cheng Chang, Ya-Yu Yang, Yu-Jiun Shen, Jen-Inn Chyi
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Patent number: 10734509Abstract: A nitride semiconductor epitaxial stack structure including: a silicon substrate; an AlN nucleation layer disposed on the silicon substrate; a buffer structure disposed on the aluminum-including nucleation layer and sequentially including a first superlattice epitaxial structure, a first GaN-based layer disposed on the first superlattice epitaxial structure, and a second superlattice epitaxial structure disposed on the first GaN based layer; a channel layer disposed on the buffer structure; and a barrier layer disposed on the channel layer; wherein the first superlattice epitaxial structure includes a first average Al composition ratio, the first GaN-based layer includes a first Al composition ratio, the_second superlattice epitaxial structure includes a second average Al composition ratio; wherein an Al composition ratio of the AlN nucleation layer?the first average Al composition ratio of the first superlattice epitaxial structure>the first Al composition ratio of the first GaN based layer>the secondType: GrantFiled: July 15, 2019Date of Patent: August 4, 2020Assignee: Epistar CorporationInventors: Shang Ju Tu, Ya Yu Yang, Chia Cheng Liu, Tsung Cheng Chang
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Publication number: 20200006543Abstract: A high electron mobility transistor, includes a substrate; a channel layer formed on the substrate; a barrier layer formed on the channel layer; a source electrode and a drain electrode formed on the barrier layer; a depletion layer formed on the barrier layer and between the source electrode and the drain electrode, wherein a material of the depletion layer comprises boron nitride or zinc oxide; and a gate electrode formed on the depletion layer.Type: ApplicationFiled: June 26, 2019Publication date: January 2, 2020Inventors: Shang-Ju TU, Chia-Cheng LIU, Tsung-Cheng CHANG, Ya-Yu YANG, Yu-Jiun SHEN, Jen-Inn CHYI
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Publication number: 20190341479Abstract: A nitride semiconductor epitaxial stack structure including: a silicon substrate; an AlN nucleation layer disposed on the silicon substrate; a buffer structure disposed on the aluminum-including nucleation layer and sequentially including a first superlattice epitaxial structure, a first GaN-based layer disposed on the first superlattice epitaxial structure, and a second superlattice epitaxial structure disposed on the first GaN based layer; a channel layer disposed on the buffer structure; and a barrier layer disposed on the channel layer; wherein the first superlattice epitaxial structure includes a first average Al composition ratio, the first GaN-based layer includes a first Al composition ratio, the_second superlattice epitaxial structure includes a second average Al composition ratio; wherein an Al composition ratio of the AlN nucleation layer?the first average Al composition ratio of the first superlattice epitaxial structure>the first Al composition ratio of the first GaN based layer>the secondType: ApplicationFiled: July 15, 2019Publication date: November 7, 2019Inventors: SHANG JU TU, YA YU YANG, CHIA CHENG LIU, TSUNG CHENG CHANG
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Patent number: 10396191Abstract: A semiconductor device, including: a channel layer formed on a substrate; a top barrier layer formed on the channel layer, wherein a first heterojunction is formed between the channel layer and the top barrier layer so that a first two-dimensional electron gas is generated in the channel layer; a buffer structure formed between the substrate and the channel layer; a back barrier layer formed between the buffer structure and the channel layer, wherein a second heterojunction is formed between the buffer structure and the back barrier layer so that a second two-dimensional electron gas is generated in the buffer structure; and a source electrode, a drain electrode, and a gate electrode formed on the top barrier layer, respectively; wherein a sheet carrier density of the second two-dimensional electron gas is less than 8E+10 cm?2.Type: GrantFiled: June 29, 2018Date of Patent: August 27, 2019Assignee: Epistar CorporationInventors: Ya-Yu Yang, Chia-Cheng Lui, Shang-Ju Tu
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Patent number: 10361295Abstract: A nitride semiconductor epitaxial stack structure including: a Silicon substrate; an aluminum-including nucleation layer disposed on the silicon substrate; a buffer structure disposed on the aluminum-including nucleation layer and sequentially including: a first superlattice epitaxial structure, a first GaN based thick layer disposed on the first superlattice epitaxial structure, a second superlattice epitaxial structure disposed on the first GaN based thick layer, and a second GaN based thick layer disposed on the second superlattice epitaxial structure; a channel layer disposed on the buffer structure; a barrier layer disposed on the channel layer; and a two dimensional electron gas layer disposed near an interface between the channel layer and the barrier layer, wherein the total thickness of the first GaN based thick layer and the second GaN based thick layer is more than 2 micrometers.Type: GrantFiled: February 22, 2018Date of Patent: July 23, 2019Assignee: EPISTAR CORPORATIONInventors: Shang Ju Tu, Ya Yu Yang, Chia Cheng Liu, Tsung Cheng Chang
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Publication number: 20190103482Abstract: A semiconductor power device includes a substrate, a buffer structure formed on the substrate, a barrier structure formed on the buffer structure, a channel layer formed on the barrier structure, and a barrier layer formed on the channel layer. The barrier structure includes a first functional layer on the buffer structure, a first back-barrier layer on the first functional layer, and an interlayer between the first back-barrier layer and the first functional layer. A material of the first back-barrier layer comprises Alx1Ga1-x1N, a material of the first functional layer comprises Alx2Ga1-x2N, 0<x1?1, 0?x2?1, and x1?x2. The interlayer includes a carbon doped or an iron doped material.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Inventors: Ya-Yu YANG, Shang-Ju TU, Tsung-Cheng CHANG, Chia-Cheng LIU
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Publication number: 20190006501Abstract: A semiconductor device, including: a channel layer formed on a substrate; a top barrier layer formed on the channel layer, wherein a first heterojunction is formed between the channel layer and the top barrier layer so that a first two-dimensional electron gas is generated in the channel layer; a buffer structure formed between the substrate and the channel layer; a back barrier layer formed between the buffer structure and the channel layer, wherein a second heterojunction is formed between the buffer structure and the back barrier layer so that a second two-dimensional electron gas is generated in the buffer structure; and a source electrode, a drain electrode, and a gate electrode formed on the top barrier layer, respectively; wherein a sheet carrier density of the second two-dimensional electron gas is less than 8E+10 cm?2.Type: ApplicationFiled: June 29, 2018Publication date: January 3, 2019Inventors: Ya-Yu Yang, Chia-Cheng Lui, Shang-Ju Tu
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Patent number: 10121886Abstract: This application provides a high power semiconductor device, which is characterized by forming two diodes connected in parallel and a schottky contact on a channel layer to lower the turn-on voltage and turn-on resistance of the high power semiconductor device at the same time and to enhance the breakdown voltage.Type: GrantFiled: July 31, 2017Date of Patent: November 6, 2018Assignee: EPISTAR CORPORATIONInventors: Ming-Chin Chen, Yi-Chih Lin, Shang-Ju Tu
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Publication number: 20180240901Abstract: A nitride semiconductor epitaxial stack structure including: a Silicon substrate; an aluminum-including nucleation layer disposed on the silicon substrate; a buffer structure disposed on the aluminum-including nucleation layer and sequentially including: a first superlattice epitaxial structure, a first GaN based thick layer disposed on the first superlattice epitaxial structure, a second superlattice epitaxial structure disposed on the first GaN based thick layer, and a second GaN based thick layer disposed on the second superlattice epitaxial structure; a channel layer disposed on the buffer structure; a barrier layer disposed on the channel layer; and a two dimensional electron gas layer disposed near an interface between the channel layer and the barrier layer, wherein the total thickness of the first GaN based thick layer and the second GaN based thick layer is more than 2 micrometers.Type: ApplicationFiled: February 22, 2018Publication date: August 23, 2018Inventors: SHANG JU TU, YA YU YANG, CHIA CHENG LIU, TSUNG CHENG CHANG
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Publication number: 20180033880Abstract: This application provides a high power semiconductor device, which is characterized by forming two diodes connected in parallel and a schottky contact on a channel layer to lower the turn-on voltage and turn-on resistance of the high power semiconductor device at the same time and to enhance the breakdown voltage.Type: ApplicationFiled: July 31, 2017Publication date: February 1, 2018Inventors: Ming-Chin CHEN, Yi-Chih LIN, Shang-Ju TU
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Patent number: 9786775Abstract: Disclosure includes a normally-off field-effect semiconductor device and the fabrication method thereof. An antigrowth portion is formed on a template. A first semiconductor layer and a second semiconductor layer on the template form two heterojunctions for creating two-dimensional electron gas regions, while a heterojunction-free area defined by the antigrowth portion separate the heterojunctions. A dielectric layer is on the second semiconductor layer and above the antigrowth portion. Two channel electrodes formed on the second semiconductor layer are electrically coupled to the two-dimensional electron gas regions respectively. A gate electrode on the dielectric layer and above the antigrowth portion is used for control of conduction between the channel electrodes.Type: GrantFiled: November 27, 2015Date of Patent: October 10, 2017Assignee: EPISTAR CORPORATIONInventor: Shang-Ju Tu
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Publication number: 20170154987Abstract: Disclosure includes a normally-off field-effect semiconductor device and the fabrication method thereof. An antigrowth portion is formed on a template. A first semiconductor layer and a second semiconductor layer on the template form two heterojunctions for creating two-dimensional electron gas regions, while a heterojunction-free area defined by the antigrowth portion separate the heterojunctions. A dielectric layer is on the second semiconductor layer and above the antigrowth portion. Two channel electrodes formed on the second semiconductor layer are electrically coupled to the two-dimensional electron gas regions respectively. A gate electrode on the dielectric layer and above the antigrowth portion is used for control of conduction between the channel electrodes.Type: ApplicationFiled: November 27, 2015Publication date: June 1, 2017Inventor: Shang-Ju TU