Patents by Inventor Shang-Hoon Seo
Shang-Hoon Seo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240178122Abstract: A semiconductor package, including a first redistribution substrate, a semiconductor chip on the first redistribution substrate, a connection structure on the first redistribution substrate and spaced apart from the semiconductor chip, the connection structure including a connection substrate and a post on the connection substrate, a second redistribution substrate on the semiconductor chip and the connection structure, and a molding layer between the first redistribution substrate and the second redistribution substrate, the molding layer encapsulating the semiconductor chip and the connection structure, wherein the connection substrate includes a conductive pattern that vertically penetrates the connection substrate, the post is in contact with a top surface of the conductive pattern, and a width of the post is less than a width of the connection substrate.Type: ApplicationFiled: July 26, 2023Publication date: May 30, 2024Inventors: Kyung Don MUN, Sangjin BAEK, Kyoung Lim SUK, Shang-Hoon SEO, Inhyung SONG, Yeonho JANG
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Publication number: 20230268266Abstract: A fan-out semiconductor package includes: an interconnection member including a first insulating layer, first and second pads respectively disposed on opposite sides of the first insulating layer, and a first via connecting the first and second pads to each other; a semiconductor chip disposed on the interconnection member; and an encapsulant encapsulating at least portions of the semiconductor chip. At least a portion of a first wall of a first trench of the first insulating layer and at least a portion of a second wall of a second trench of the second insulating layer overlap each other vertically.Type: ApplicationFiled: March 20, 2023Publication date: August 24, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun Ho Kim, Ji Hoon Kim, Ha Young Ahn, Shang Hoon Seo, Seung Yeop Kook, Sung Won Jeong
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Patent number: 11626364Abstract: A fan-out semiconductor package includes: an interconnection member including a first insulating layer, first and second pads respectively disposed on opposite sides of the first insulating layer and a first via connecting the first and second pads to each other; a semiconductor chip disposed on the interconnection member; and an encapsulant encapsulating at least portions of the semiconductor chip. A center line of the first via is out of alignment with at least one of a center line of the first pad and a center line of the second pad.Type: GrantFiled: December 7, 2020Date of Patent: April 11, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun Ho Kim, Ji Hoon Kim, Ha Young Ahn, Shang Hoon Seo, Seung Yeop Kook, Sung Won Jeong
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Publication number: 20230026972Abstract: Disclosed are semiconductor packages and their fabricating methods. The semiconductor package includes a lower structure and an upper redistribution layer. The lower structure includes a first bump layer, a lower redistribution layer, a semiconductor chip, a molding layer, a conductive pillar, and an under pad layer. The upper redistribution layer includes a second bump layer and second redistribution layers. The first redistribution layer includes a lower redistribution pattern including a first line part and a first via part. A width of the first via part increases in a direction toward the first line part from a bottom surface of the first via part. The second redistribution layer includes an upper redistribution pattern including a second line part and the second via part. A width of the second via part increases in a direction toward the second line part from a top surface of the second via part.Type: ApplicationFiled: March 22, 2022Publication date: January 26, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Yeonho JANG, Dongkyu KIM, Shang-Hoon SEO, Jaegwon JANG
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Publication number: 20210118791Abstract: A fan-out semiconductor package includes: an interconnection member including a first insulating layer, first and second pads respectively disposed on opposite sides of the first insulating layer and a first via connecting the first and second pads to each other; a semiconductor chip disposed on the interconnection member; and an encapsulant encapsulating at least portions of the semiconductor chip. A center line of the first via is out of alignment with at least one of a center line of the first pad and a center line of the second pad.Type: ApplicationFiled: December 7, 2020Publication date: April 22, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun Ho Kim, Ji Hoon Kim, Ha Young Ahn, Shang Hoon Seo, Seung Yeop Kook, Sung Won Jeong
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Patent number: 10985127Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a stopper layer; a semiconductor chip having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface, and disposed in the recess portion so that the inactive surface is connected to the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers of the frame and the connection pads of the semiconductor chip to each other, wherein the stopper layer includes an insulating material.Type: GrantFiled: November 27, 2019Date of Patent: April 20, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jeong Ho Lee, Bong Ju Cho, Young Gwan Ko, Jin Su Kim, Shang Hoon Seo, Jeong Il Lee
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Patent number: 10861784Abstract: A fan-out semiconductor package includes: an interconnection member including a first insulating layer, first and second pads respectively disposed on opposite sides of the first insulating layer and a first via connecting the first and second pads to each other; a semiconductor chip disposed on the interconnection member; and an encapsulant encapsulating at least portions of the semiconductor chip. A center line of the first via is out of alignment with at least one of a center line of the first pad and a center line of the second pad.Type: GrantFiled: May 27, 2020Date of Patent: December 8, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun Ho Kim, Ji Hoon Kim, Ha Young Ahn, Shang Hoon Seo, Seung Yeop Kook, Sung Won Jeong
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Publication number: 20200294904Abstract: A fan-out semiconductor package includes: an interconnection member including a first insulating layer, first and second pads respectively disposed on opposite sides of the first insulating layer and a first via connecting the first and second pads to each other; a semiconductor chip disposed on the interconnection member; and an encapsulant encapsulating at least portions of the semiconductor chip. A center line of the first via is out of alignment with at least one of a center line of the first pad and a center line of the second pad.Type: ApplicationFiled: May 27, 2020Publication date: September 17, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun Ho KIM, Ji Hoon KIM, Ha Young AHN, Shang Hoon SEO, Seung Yeop KOOK, Sung Won JEONG
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Patent number: 10679933Abstract: A fan-out semiconductor package includes: an interconnection member including a first insulating layer, first and second pads respectively disposed on opposite sides of the first insulating layer and a first via connecting the first and second pads to each other; a semiconductor chip disposed on the interconnection member; and an encapsulant encapsulating at least portions of the semiconductor chip. A center line of the first via is out of alignment with at least one of a center line of the first pad and a center line of the second pad.Type: GrantFiled: October 10, 2019Date of Patent: June 9, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun Ho Kim, Ji Hoon Kim, Ha Young Ahn, Shang Hoon Seo, Seung Yeop Kook, Sung Won Jeong
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Publication number: 20200126942Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a stopper layer; a semiconductor chip having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface, and disposed in the recess portion so that the inactive surface is connected to the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers of the frame and the connection pads of the semiconductor chip to each other, wherein the stopper layer includes an insulating material.Type: ApplicationFiled: November 27, 2019Publication date: April 23, 2020Applicant: SAMSUNG ELECTRONICS CO., LTDInventors: Jeong Ho LEE, Bong Ju CHO, Young Gwan KO, Jin Su Kim, Shang Hoon SEO, Jeong II LEE
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Publication number: 20200043842Abstract: A fan-out semiconductor package includes: an interconnection member including a first insulating layer, first and second pads respectively disposed on opposite sides of the first insulating layer and a first via connecting the first and second pads to each other; a semiconductor chip disposed on the interconnection member; and an encapsulant encapsulating at least portions of the semiconductor chip. A center line of the first via is out of alignment with at least one of a center line of the first pad and a center line of the second pad.Type: ApplicationFiled: October 10, 2019Publication date: February 6, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun Ho KIM, Ji Hoon Kim, Ha Young Ahn, Shang Hoon Seo, Seung Yeop Kook, Sung Won Jeong
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Patent number: 10522497Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a stopper layer; a semiconductor chip having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface, and disposed in the recess portion so that the inactive surface is connected to the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers of the frame and the connection pads of the semiconductor chip to each other, wherein the stopper layer includes an insulating material.Type: GrantFiled: May 24, 2018Date of Patent: December 31, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jeong Ho Lee, Bong Ju Cho, Young Gwan Ko, Jin Su Kim, Shang Hoon Seo, Jeong Il Lee
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Patent number: 10475748Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a stopper layer; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is connected to the stopper layer; a first encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; an electronic component disposed on the other surface of the frame opposing one surface of the frame in which the semiconductor chip is disposed; a second encapsulant covering at least portions of the electronic component; and a connection member disposed on the frame and an active surface of the semiconductor chip and including a redistribution layer, wherein the connection pads and the electronic component are electrically connected to each other through the wiring layers and the redistribution layer.Type: GrantFiled: May 16, 2018Date of Patent: November 12, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jeong Ho Lee, Myung Sam Kang, Young Gwan Ko, Shang Hoon Seo, Jin Su Kim
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Patent number: 10461008Abstract: An electronic component package includes a wiring part including an insulating layer, a conductive pattern formed on the insulating layer, and a conductive via connected to the conductive pattern through the insulating layer, an electronic component disposed on the wiring part, a frame disposed on the wiring part and having a component disposition region defined by an inner wall of the frame surrounding the electronic component, and an encapsulant filling at least a portion of the component disposition region. A portion of the inner wall of the frame forms a protrusion protruding toward the electronic component.Type: GrantFiled: July 8, 2016Date of Patent: October 29, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung Won Jeong, Ji Hoon Kim, Sun Ho Kim, Shang Hoon Seo, Seung Yeop Kook, Christian Romero
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Patent number: 10446481Abstract: A fan-out semiconductor package includes: an interconnection member including a first insulating layer, first and second pads respectively disposed on opposite sides of the first insulating layer and a first via connecting the first and second pads to each other; a semiconductor chip disposed on the interconnection member; and an encapsulant encapsulating at least portions of the semiconductor chip. A center line of the first via is out of alignment with at least one of a center line of the first pad and a center line of the second pad.Type: GrantFiled: July 18, 2018Date of Patent: October 15, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun Ho Kim, Ji Hoon Kim, Ha Young Ahn, Shang Hoon Seo, Seung Yeop Kook, Sung Won Jeong
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Patent number: 10410961Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion, and having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface and disposed on the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the plurality of wiring layers of the frame and the connection pads of the semiconductor chip to each other. The active surface of the semiconductor chip and an upper surface of the encapsulant have a step portion therebetween.Type: GrantFiled: May 14, 2018Date of Patent: September 10, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jeong Ho Lee, Myung Sam Kang, Young Gwan Ko, Jin Su Kim, Shang Hoon Seo, Jeong Il Lee
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Patent number: 10347586Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is disposed on the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; a connection member disposed on the frame and an active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers and the connection pads to each other; and a guide pattern disposed adjacent to a wall of the recess portion and disposed in the frame. An edge of the bottom surface of the recess portion has a groove portion.Type: GrantFiled: May 22, 2018Date of Patent: July 9, 2019Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Jin Su Kim, Jeong Ho Lee, Shang Hoon Seo, Bong Ju Cho
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Publication number: 20190198429Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is disposed on the stopper layer; first metal bumps disposed on the connection pads; an encapsulant covering at least portions of each of the frame, the semiconductor chip, and the first metal bumps and filling at least portions of the recess portion; a connection member disposed on the frame and an active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers and the connection pads to each other; and a first blocking structure disposed on walls of the recess portion to surround side surfaces of the semiconductor chip.Type: ApplicationFiled: June 19, 2018Publication date: June 27, 2019Inventors: Myung Sam KANG, Young Gwan KO, Jeong Ho LEE, Shang Hoon SEO, Yong Jin SEOL
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Publication number: 20190164895Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is disposed on the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; a connection member disposed on the frame and an active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers and the connection pads to each other; and a guide pattern disposed adjacent to a wall of the recess portion and disposed in the frame. An edge of the bottom surface of the recess portion has a groove portion.Type: ApplicationFiled: May 22, 2018Publication date: May 30, 2019Inventors: Jin Su KIM, Jeong Ho LEE, Shang Hoon SEO, Bong Ju CHO
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Publication number: 20190131253Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a stopper layer; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is connected to the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and an active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers of the frame and the connection pads of the semiconductor chip to each other. A lowermost wiring layer of the wiring layers is embedded in the frame and has a lower surface exposed from a lowermost insulating layer of the frame.Type: ApplicationFiled: May 14, 2018Publication date: May 2, 2019Inventors: Jeong Ho LEE, Myung Sam KANG, Young Gwan KO, Shang Hoon SEO, Jin Su KIM