Patents by Inventor Shang-Wei Fang
Shang-Wei Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11916070Abstract: Disclosed are semiconductor devices including a substrate, a first transistor formed over a first portion of the substrate, wherein the first transistor comprises a first nanosheet stack including N nanosheets and a second transistor over a second portion of the substrate, wherein the second transistor comprises a second nanosheet stack including M nanosheets, wherein N is different from M in which the first and second nanosheet stacks are formed on first and second substrate regions that are vertically offset from one another.Type: GrantFiled: June 11, 2021Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Te-Hsin Chiu, Kam-Tou Sio, Shang-Wei Fang, Wei-Cheng Lin, Jiann-Tyng Tzeng
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Patent number: 11893333Abstract: A method of generating an IC layout diagram includes abutting a first row of cells with a second row of cells along a border, the first row including first and second active sheets, the second row including third and fourth active sheets, the active sheets extending along a row direction and having width values. The active sheets are overlapped with first through fourth back-side via regions, the first active sheet width value is greater than the third active sheet width value, a first back-side via region width values is greater than a third back-side via region width value, and a value of a distance from the first active sheet to the border is less than a minimum spacing rule for metal-like defined regions. At least one of abutting the first row with the second row or overlapping the active sheets with the back-side via regions is performed by a processor.Type: GrantFiled: January 13, 2021Date of Patent: February 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shang-Wei Fang, Kam-Tou Sio, Wei-Cheng Lin, Jiann-Tyng Tzeng, Lee-Chung Lu, Yi-Kan Cheng, Chung-Hsing Wang
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Publication number: 20240014281Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes: at least one gate structure having a first side and a second side opposite to each other; a first source/drain (S/D) feature disposed at the first side of the at least one gate structure; a second S/D feature disposed at the second side of the at least one gate structure; a first metal-to-drain/source (MD) contact disposed on the first S/D feature; and a second MD contact disposed on the second S/D feature, wherein a contact area between the first MD contact and the first S/D feature is greater than a contact area between the second MD contact and the second S/D feature.Type: ApplicationFiled: July 11, 2022Publication date: January 11, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Feng Huang, Kam-Tou Sio, Jiann-Tyng Tzeng, Shang-Wei Fang, Chun-Yen Lin
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Publication number: 20230411389Abstract: Disclosed are semiconductor devices including a substrate, a first transistor formed over a first portion of the substrate, wherein the first transistor comprises a first nanosheet stack including N nanosheets and a second transistor over a second portion of the substrate, wherein the second transistor comprises a second nanosheet stack including M nanosheets, wherein N is different from M in which the first and second nanosheet stacks are formed on first and second substrate regions that are vertically offset from one another.Type: ApplicationFiled: August 10, 2023Publication date: December 21, 2023Inventors: Te-Hsin CHIU, Kam-Tou SIO, Shang-Wei FANG, Wei-Cheng LIN, Jiann-Tyng TZENG
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Publication number: 20230401372Abstract: An integrated circuit (IC) includes first through fourth nano-sheet structures extending in a first direction and having respective first through fourth widths along a second direction perpendicular to the first direction, and first through fourth via structures electrically connected to corresponding ones of the first through fourth nano-sheet structures. The second width has a value greater than that of the third width. A width of the second via structure along the second direction has a value greater than that of a width of the third via structure along the second direction. The second and third nano-sheet structures are positioned between the first and fourth nano-sheet structures. The second and third via structures are configured to electrically connect the second and third nano-sheet structures to a first portion of a back-side power distribution structure configured to carry one of a power supply voltage or a reference voltage.Type: ApplicationFiled: August 10, 2023Publication date: December 14, 2023Inventors: Shang-Wei FANG, Kam-Tou SIO, Wei-Cheng LIN, Jiann-Tyng TZENG, Lee-Chung LU, Yi-Kan CHENG, Chung-Hsing WANG
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Publication number: 20230275090Abstract: A semiconductor device includes a first cell in a first row, wherein the first row extends in a first direction, the first cell having a first cell height measured in a second direction perpendicular to the first direction. The semiconductor device further includes a second cell in the first row, wherein the second cell has a second cell height measured in the second direction, the second cell height is less than the first cell height. The second cell includes a first active region having a first width measured in the second direction, and a second active region having a second width measured in the second direction, wherein the second width is different from the first width.Type: ApplicationFiled: June 10, 2022Publication date: August 31, 2023Inventors: Jiann-Tyng TZENG, Kam-Tou SIO, Shang-Wei FANG, Chun-Yen LIN, Sheng-Feng HUANG, Yi-Kan CHENG, Lee-Chung LU
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Publication number: 20230253403Abstract: An integrated circuit device includes: a first fin structure disposed on a substrate in a first direction; a second fin structure disposed on the substrate and aligned in the first direction; a third fin structure disposed on the substrate and aligned in the first direction; and a first conductive line aligned in a second direction arranged to wrap a first portion, a second portion, and a third portion of the first fin structure, the second fin structure and the third fin structure, respectively. Each of the first fin structure, the second fin structure and the third fin structure has a same type dopant. A first distance between the first fin structure and the second fin structure is different from a second distance between the second fin structure and the third fin structure.Type: ApplicationFiled: April 18, 2023Publication date: August 10, 2023Inventors: KAM-TOU SIO, SHANG-WEI FANG, JIANN-TYNG TZENG, CHEW-YUEN YOUNG
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Patent number: 11658182Abstract: An integrated circuit device includes: a first fin structure disposed on a substrate in a first direction; a second fin structure disposed on the substrate and aligned in the first direction; a third fin structure disposed on the substrate and aligned in the first direction; and a first conductive line aligned in a second direction arranged to wrap a first portion, a second portion, and a third portion of the first fin structure, the second fin structure and the third fin structure, respectively. Each of the first fin structure, the second fin structure and the third fin structure has a same type dopant. A first distance between the first fin structure and the second fin structure is different from a second distance between the second fin structure and the third fin structure.Type: GrantFiled: March 23, 2021Date of Patent: May 23, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Kam-Tou Sio, Shang-Wei Fang, Jiann-Tyng Tzeng, Chew-Yuen Young
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Publication number: 20220238515Abstract: An integrated circuit is provided, including a first conductive pattern, at least one first conductive segment, and a first via. The first conductive pattern is disposed in a first layer and configured as a terminal of an inverter. The at least one first conductive segment is disposed in a second layer above the first layer and configured to transmit an output signal output from the inverter. The first via contacts the first conductive pattern and the at least one first conductive segment to transmit the output signal. An area, contacting the first conductive pattern, of the first via is smaller than an area, contacting the at least one first conductive segment, of the first via.Type: ApplicationFiled: April 13, 2022Publication date: July 28, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Po-Chia LAI, Shang-Wei FANG, Meng-Hung SHEN, Jiann-Tyng TZENG, Ting-Wei CHIANG, Jung-Chan YANG, Stefan RUSU
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Publication number: 20220130822Abstract: Disclosed are semiconductor devices including a substrate, a first transistor formed over a first portion of the substrate, wherein the first transistor comprises a first nanosheet stack including N nanosheets and a second transistor over a second portion of the substrate, wherein the second transistor comprises a second nanosheet stack including M nanosheets, wherein N is different from M in which the first and second nanosheet stacks are formed on first and second substrate regions that are vertically offset from one another.Type: ApplicationFiled: June 11, 2021Publication date: April 28, 2022Inventors: Te-Hsin CHIU, Kam-Tou SIO, Shang-Wei FANG, Wei-Cheng LIN, Jiann-Tyng TZENG
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Patent number: 11309311Abstract: An integrated circuit is disclosed, including a first conductive pattern and a second conductive pattern that are disposed in a first layer and extend in a first direction, at least one first conductive segment disposed in a second layer different from the first layer, and at least one via disposed between the first layer and the second layer. The at least one via is coupled between the at least one first conductive segment and one or both of the first conductive pattern and the second conductive pattern, at an output node of the integrated circuit. The at least one via comprises a tapered shape with a width that decreases from a first width to a second width narrower than the first width. The first width of the at least one via is greater than widths of the first conductive pattern and the second conductive pattern.Type: GrantFiled: February 11, 2020Date of Patent: April 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Po-Chia Lai, Shang-Wei Fang, Meng-Hung Shen, Jiann-Tyng Tzeng, Ting-Wei Chiang, Jung-Chan Yang, Stefan Rusu
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Publication number: 20210357565Abstract: A method of generating an IC layout diagram includes abutting a first row of cells with a second row of cells along a border, the first row including first and second active sheets, the second row including third and fourth active sheets, the active sheets extending along a row direction and having width values. The active sheets are overlapped with first through fourth back-side via regions, the first active sheet width value is greater than the third active sheet width value, a first back-side via region width values is greater than a third back-side via region width value, and a value of a distance from the first active sheet to the border is less than a minimum spacing rule for metal-like defined regions. At least one of abutting the first row with the second row or overlapping the active sheets with the back-side via regions is performed by a processor.Type: ApplicationFiled: January 13, 2021Publication date: November 18, 2021Inventors: Shang-Wei FANG, Kam-Tou SIO, Wei-Cheng LIN, Jiann-Tyng TZENG, Lee-Chung LU, Yi-Kan CHENG, Chung-Hsing WANG
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Patent number: 11152348Abstract: An integrated circuit structure includes: a first plurality of cell rows extending in a first direction, each of which has a first row height and comprises a plurality of first cells disposed therein; and a second plurality of cell rows extending in the first direction, each of which has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction, and wherein the plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction.Type: GrantFiled: November 20, 2018Date of Patent: October 19, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kam-Tou Sio, Jiann-Tyng Tzeng, Jack Liu, Yi-Chuin Tsai, Shang-Wei Fang, Sing-Kai Huang, Charles Chew-Yuen Young
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Publication number: 20210249407Abstract: An integrated circuit is disclosed, including a first conductive pattern and a second conductive pattern that are disposed in a first layer and extend in a first direction, at least one first conductive segment disposed in a second layer different from the first layer, and at least one via disposed between the first layer and the second layer. The at least one via is coupled between the at least one first conductive segment and one or both of the first conductive pattern and the second conductive pattern, at an output node of the integrated circuit. The at least one via comprises a tapered shape with a width that decreases from a first width to a second width narrower than the first width. The first width of the at least one via is greater than widths of the first conductive pattern and the second conductive pattern.Type: ApplicationFiled: February 11, 2020Publication date: August 12, 2021Inventors: Po-Chia LAI, Shang-Wei FANG, Meng-Hung SHEN, Jiann-Tyng TZENG, Ting-Wei CHIANG, Jung-Chan YANG, Stefan RUSU
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Publication number: 20210210488Abstract: An integrated circuit device includes: a first fin structure disposed on a substrate in a first direction; a second fin structure disposed on the substrate and aligned in the first direction; a third fin structure disposed on the substrate and aligned in the first direction; and a first conductive line aligned in a second direction arranged to wrap a first portion, a second portion, and a third portion of the first fin structure, the second fin structure and the third fin structure, respectively. Each of the first fin structure, the second fin structure and the third fin structure has a same type dopant. A first distance between the first fin structure and the second fin structure is different from a second distance between the second fin structure and the third fin structure.Type: ApplicationFiled: March 23, 2021Publication date: July 8, 2021Inventors: KAM-TOU SIO, SHANG-WEI FANG, JIANN-TYNG TZENG, CHEW-YUEN YOUNG
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Patent number: 10971493Abstract: An integrated circuit device includes: a first fin structure disposed on a substrate in a first direction; a second fin structure disposed on the substrate and aligned in the first direction; a third fin structure disposed on the substrate and aligned in the first direction; a fourth fin structure disposed on the substrate and aligned in the first direction; and a first conductive line aligned in a second direction arranged to wrap a first portion, a second portion, a third portion, and a fourth portion of the first fin structure, the second fin structure, the third fin structure, and the fourth fin structure respectively. A first distance between the first fin structure and the second fin structure is different from a second distance between the third fin structure and the fourth fin structure.Type: GrantFiled: June 14, 2018Date of Patent: April 6, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Kam-Tou Sio, Shang-Wei Fang, Jiann-Tyng Tzeng, Chew-Yuen Young
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Patent number: 10879135Abstract: A method for inline inspection during semiconductor wafer fabrication is provided. The method includes forming a plurality of test structures on a semiconductor wafer along two opposite directions. An offset distance between a sample feature and a target feature of each of the test structures increases gradually along the two opposite directions. The method further includes producing an image of the test structures. The method also includes performing image analysis of the image to recognize a position with an extreme of a gray level. In addition, the method includes calculating an overlay error according to the recognized position.Type: GrantFiled: December 16, 2019Date of Patent: December 29, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Shang-Wei Fang, Jing-Sen Wang, Yuan-Yao Chang, Wei-Ray Lin, Ting-Hua Hsieh, Pei-Hsuan Lee, Yu-Hsuan Huang
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Publication number: 20200118893Abstract: A method for inline inspection during semiconductor wafer fabrication is provided. The method includes forming a plurality of test structures on a semiconductor wafer along two opposite directions. An offset distance between a sample feature and a target feature of each of the test structures increases gradually along the two opposite directions. The method further includes producing an image of the test structures. The method also includes performing image analysis of the image to recognize a position with an extreme of a gray level. In addition, the method includes calculating an overlay error according to the recognized position.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Inventors: Shang-Wei FANG, Jing-Sen WANG, Yuan-Yao CHANG, Wei-Ray LIN, Ting-Hua HSIEH, Pei-Hsuan LEE, Yu-Hsuan HUANG
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Patent number: 10510623Abstract: A method for inline inspection during semiconductor wafer fabrication is provided. The method includes forming a plurality of test structures on a semiconductor wafer along two opposite directions. An offset distance between a sample feature and a target feature of each of the test structures increases gradually along the two opposite directions. The method further includes producing an image of the test structures. The method also includes performing image analysis of the image to recognize a position with an extreme of a gray level. In addition, the method includes calculating an overlay error according to the recognized position.Type: GrantFiled: December 27, 2017Date of Patent: December 17, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shang-Wei Fang, Jing-Sen Wang, Yuan-Yao Chang, Wei-Ray Lin, Ting-Hua Hsieh, Pei-Hsuan Lee, Yu-Hsuan Huang
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Publication number: 20190198403Abstract: A method for inline inspection during semiconductor wafer fabrication is provided. The method includes forming a plurality of test structures on a semiconductor wafer along two opposite directions. An offset distance between a sample feature and a target feature of each of the test structures increases gradually along the two opposite directions. The method further includes producing an image of the test structures. The method also includes performing image analysis of the image to recognize a position with an extreme of a gray level. In addition, the method includes calculating an overlay error according to the recognized position.Type: ApplicationFiled: December 27, 2017Publication date: June 27, 2019Inventors: Shang-Wei FANG, Jing-Sen WANG, Yuan-Yao CHANG, Wei-Ray LIN, Ting-Hua HSIEH, Pei-Hsuan LEE, Yu-Hsuan HUANG