Patents by Inventor Shankar Channabasappa

Shankar Channabasappa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9178692
    Abstract: A method is disclosed for handling packet data. The method includes assembling request packets for transmission along a plurality of serial lanes. For each lane, at least a portion of the request packets are framed into a request link frame having a plurality of words. The request link frame is defined by a preset word length. Request training words are inserted into the request link frame at intervals corresponding to the preset word length. Response packets are queued, where the response packets include response training words having an associated latency based on the programmed interval of the request training words.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: November 3, 2015
    Assignee: BROADCOM CORPORATION
    Inventor: Shankar Channabasappa
  • Patent number: 9025354
    Abstract: A content search system including a CAM device having a plurality of CAM blocks and a governor logic receives a search request and compares the number of CAM blocks required to perform the requested search to a limit number, the limit number being the maximum number of CAM blocks permitted to be used in a requested search operation. If the number of CAM blocks required to perform the requested search exceeds the maximum number of CAM blocks permitted to be used in a requested search operation, then the search operation is rejected. The governing operation can be performed on each requested search, thus limiting power dissipation. The relationship between a maximum number of CAM blocks and power dissipation can be characterized, and a corresponding block limit value can be stored into a memory accessible by governor logic.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: May 5, 2015
    Assignee: Broadcom Corporation
    Inventor: Shankar Channabasappa
  • Patent number: 8990631
    Abstract: Approaches for a packet format for error reporting in a content addressable memory (CAM) device are disclosed. The CAM device may comprise a CAM array that includes a plurality of rows, each row including a plurality of CAM cells coupled to a match line, and an error notification circuit capable of forming a packet that indicates whether the CAM device is experiencing an error condition. If an error condition was experienced by the CAM device, the response packet may also indicate the type(s) of error that was encountered. Advantageously, information about any error condition experienced by the CAM device may be quickly ascertained by a host device in which the CAM device is incorporated.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: March 24, 2015
    Assignee: Netlogic Microsystems, Inc.
    Inventor: Shankar Channabasappa
  • Patent number: 8848526
    Abstract: An integrated circuit is disclosed. The integrated circuit includes a receive port interface to receive request data at a first data rate from a first host and a transmit port interface. The transmit port interface to transmit response data words across plural serial lanes to a second host at a second data rate. The second data rate is less than a predefined line rate of symbol transfers across the plural serial lanes. The transmit port interface includes shaping logic to transmit a data word stream at the second data rate and selectively insert idle words into the data word stream such that the data words and the idle words are together transferred at the predefined line rate.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: September 30, 2014
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Shankar Channabasappa, Amit Arora
  • Patent number: 8792348
    Abstract: A receiver circuit for coupling to a serial link is disclosed. The receiver circuit comprises a data buffer and serial interface circuitry. The serial interface circuitry receives serialized packet words and processes the serial words for input to the data buffer. The serial interface circuitry includes word detection logic to detect predefined control words and discard logic to selectively inhibit forwarding of one or more of the predefined control words to the data buffer.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: July 29, 2014
    Assignee: Netlogic Microsystems, Inc.
    Inventor: Shankar Channabasappa
  • Publication number: 20130279231
    Abstract: A content search system including a CAM device having a plurality of CAM blocks and a governor logic receives a search request and compares the number of CAM blocks required to perform the requested search to a limit number, the limit number being the maximum number of CAM blocks permitted to be used in a requested search operation. If the number of CAM blocks required to perform the requested search exceeds the maximum number of CAM blocks permitted to be used in a requested search operation, then the search operation is rejected. The governing operation can be performed on each requested search, thus limiting power dissipation. The relationship between a maximum number of CAM blocks and power dissipation can be characterized, and a corresponding block limit value can be stored into a memory accessible by governor logic.
    Type: Application
    Filed: June 11, 2013
    Publication date: October 24, 2013
    Inventor: Shankar CHANNABASAPPA
  • Patent number: 8467213
    Abstract: A content search system including a CAM device having a plurality of CAM blocks and a governor logic receives a search request and compares the number of CAM blocks required to perform the requested search to a limit number, the limit number being the maximum number of CAM blocks permitted to be used in a requested search operation. If the number of CAM blocks required to perform the requested search exceeds the maximum number of CAM blocks permitted to be used in a requested search operation, then the search operation is rejected. The governing operation can be performed on each requested search, thus limiting power dissipation. The relationship between a maximum number of CAM blocks and power dissipation can be characterized, and a corresponding block limit value can be stored into a memory accessible by governor logic.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: June 18, 2013
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Shankar Channabasappa
  • Patent number: 6883025
    Abstract: A multiple channel communication system includes a plurality of network communication ports, a plurality of communication devices and an autonegotiation controller. Each communication device is coupled to a respective one of the plurality of network communication ports. The autonegotiation controller is coupled to and shared by the plurality of communication devices.
    Type: Grant
    Filed: December 7, 2001
    Date of Patent: April 19, 2005
    Assignee: LSI Logic Corporation
    Inventors: Sateesh Andra, Shankar Channabasappa
  • Publication number: 20020046267
    Abstract: A multiple channel communication system includes a plurality of network communication ports, a plurality of communication devices and an autonegotiation controller. Each communication device is coupled to a respective one of the plurality of network communication ports. The autonegotiation controller is coupled to and shared by the plurality of communication devices.
    Type: Application
    Filed: December 7, 2001
    Publication date: April 18, 2002
    Inventors: Sateesh Andra, Shankar Channabasappa
  • Patent number: 6349331
    Abstract: A multiple channel communication system includes a plurality of network communication ports, a plurality of communication devices and an autonegotiation controller. Each communication device is coupled to a respective one of the plurality of network communication ports. The autonegotiation controller is coupled to and shared by the plurality of communication devices.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: February 19, 2002
    Assignee: LSI Logic Corporation
    Inventors: Sateesh Andra, Shankar Channabasappa