Abstract: A crop prediction system performs various machine learning operations to predict crop production and to identify a set of farming operations that, if performed, optimize crop production. The crop prediction system uses crop prediction models trained using various machine learning operations based on geographic and agronomic information. Responsive to receiving a request from a grower, the crop prediction system can access information representation of a portion of land corresponding to the request, such as the location of the land and corresponding weather conditions and soil composition. The crop prediction system applies one or more crop prediction models to the access information to predict a crop production and identify an optimized set of farming operations for the grower to perform.

Abstract: A memory circuit includes first and second inverters that are cross coupled. The first inverter is configured to provide a first drive current from a first supply line to store a first logic state in the memory circuit. The first drive current is larger than a second drive current that the second inverter is configured to provide from the first supply line to store a second logic state in the memory circuit.

Abstract: Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but doing so can potentially affect the performance of in-operation pass gates that are being controlled by the memory array during user mode. In one suitable arrangement, ground power supply voltage write assist techniques may be implemented on memory cells that include p-channel access transistors and that are used to control n-channel pass transistors. In another suitable arrangement, positive power supply voltage write assist techniques may be implemented on memory cells that include n-channel access transistors and that are used to control p-channel pass transistors.

Abstract: Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but doing so can potentially affect the performance of in-operation pass gates that are being controlled by the memory array during user mode. In one suitable arrangement, ground power supply voltage write assist techniques may be implemented on memory cells that include p-channel access transistors and that are used to control n-channel pass transistors. In another suitable arrangement, positive power supply voltage write assist techniques may be implemented on memory cells that include n-channel access transistors and that are used to control p-channel pass transistors.

Abstract: Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but doing so can potentially affect the performance of in-operation pass gates that are being controlled by the memory array during user mode. In one suitable arrangement, ground power supply voltage write assist techniques may be implemented on memory cells that include p-channel access transistors and that are used to control n-channel pass transistors. In another suitable arrangement, positive power supply voltage write assist techniques may be implemented on memory cells that include n-channel access transistors and that are used to control p-channel pass transistors.

Abstract: Integrated circuits with multiport memory elements may be provided. A multiport memory element may include a latching circuit, a first set of address transistors, and a second set of address transistors. The latching circuit may include cross-coupled inverters, each of which includes a pull-up transistor and a pull-down transistor. The first set of address transistors may couple the latching circuit to a write port, whereas the second set of address transistors may couple the latching circuit to a read port. The pull-down transistors and the second set of address transistors may have body bias terminals that are controlled by a control signal. During data loading operations, the control signal may be temporarily elevated to weaken the pull-down transistors and the second set of address transistors to improve the write margin of the multiport memory element.

Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

Abstract: In patterning a transistor, some of a layer of gate dielectric material is allowed to remain over a semiconductor substrate upon which the transistor is formed. This remaining dielectric material retards the implantation of dopants into the underlying substrate, effectively lengthening a channel region of the transistor. This mitigates unwanted short channel effects, such as leakage currents, for example, and thus mitigates yield loss by establishing a transistor that performs in a more predictable or otherwise desirable manner.

Abstract: Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but doing so can potentially affect the performance of in-operation pass gates that are being controlled by the memory array during user mode. In one suitable arrangement, ground power supply voltage write assist techniques may be implemented on memory cells that include p-channel access transistors and that are used to control n-channel pass transistors. In another suitable arrangement, positive power supply voltage write assist techniques may be implemented on memory cells that include n-channel access transistors and that are used to control p-channel pass transistors.

Abstract: Integrated circuits with memory cells are provided. A memory cell may include first and second cross-coupled inverting circuits configured to store a single data bit. The first inverting circuit may have an output serving as a first data storage node for the memory cell, whereas the second inverting circuit may have an output serving as a second data storage node for the memory cell. Access transistors may be coupled between the first and second data storage nodes and corresponding data lines. Each of the first and second inverting circuit may have a pull-down transistor and at least two pull-up transistors stacked in series. The pull-down transistors may have body terminals that are reverse biased to help reduce leakage current through the first and second inverting circuits. The memory cell may be formed using a narrower two-gate configuration or a wider four-gate configuration.

Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

Abstract: One embodiment of the present invention relates to a memory cell. The memory cell comprises a substrate and a stacked gate structure disposed on the substrate, wherein the stacked gate structure comprises a charge trapping dielectric layer that is adapted to store at least one bit of data. The memory cell further includes a source and drain in the substrate, wherein the source and drain are disposed at opposite sides of the stacked gate structure. A barrier region is disposed substantially beneath the source or the drain and comprises an inert species. Other embodiments are also disclosed.

Abstract: An integrated circuit with electrically programmable fuse circuitry coupled to a programming transistor is provided. The programming transistor may be a metal-oxide-semiconductor transistor that is separated from other circuitry in an integrated circuit substrate with shallow trench isolation. The electrically programmable fuse circuitry may be formed in a second layer above the integrated circuit substrate using a conductive material which may be tungsten-based. This second layer may further include interconnect wires made from the same conductive material. The electrically programmable fuse may be coupled to the programming transistor through vias and routing paths in a fourth layer above the integrated circuit substrate. The routing paths in the fourth layer may be made from a conductive material which may be different than the fuse conductive material used to form the programmable fuse circuitry.

Abstract: Integrated circuits with memory elements are provided. A memory element may include a storage circuit coupled to data lines through access transistors. Access transistors may be used to read data from and write data into the storage circuit. An access transistor may have asymmetric source-drain resistances. The access transistor may have a first source-drain that is coupled to a data line and a second source-drain that is coupled to the storage circuit. The second source-drain may have a contact resistance that is greater than the contact resistance associated with the first source-drain. Access transistors with asymmetric source-drain resistances may have a first drive strength when passing a low signal and a second drive strength when passing a high signal to the storage circuit. The second drive strength may be less than the first drive strength. Access transistors with asymmetric drive strengths may be used to improve memory read/write performance.

Abstract: Disclosed are apparatus and devices for programming and operating a programmable memory array portion coupled with a leakage reduction circuit. At the leakage reduction circuit, a frame bias signal that indicates a majority state of the memory array portion can be received. During idle states of the programmable memory array portion, at least one shared bit line of the memory array portion can be selectively biased based on the received frame bias signal. In one aspect, a first one of two bit lines is biased to a first state, while the second one of the two bits lines is biased to a second state that is opposite the first state. In a further aspect, the first state is a same state as the majority state of the memory array portion.

Abstract: Integrated circuits with multiport memory elements may be provided. A multiport memory element may include a latching circuit, a first set of address transistors, and a second set of address transistors. The latching circuit may include cross-coupled inverters, each of which includes a pull-up transistor and a pull-down transistor. The first set of address transistors may couple the latching circuit to a write port, whereas the second set of address transistors may couple the latching circuit to a read port. The pull-down transistors and the second set of address transistors may have body bias terminals that are controlled by a control signal. During data loading operations, the control signal may be temporarily elevated to weaken the pull-down transistors and the second set of address transistors to improve the write margin of the multiport memory element.

Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

Abstract: Integrated circuits with memory elements are provided. A memory element may include a storage circuit coupled to data lines through access transistors. Access transistors may be used to read data from and write data into the storage circuit. An access transistor may have asymmetric source-drain resistances. The access transistor may have a first source-drain that is coupled to a data line and a second source-drain that is coupled to the storage circuit. The second source-drain may have a contact resistance that is greater than the contact resistance associated with the first source-drain. Access transistors with asymmetric source-drain resistances may have a first drive strength when passing a low signal and a second drive strength when passing a high signal to the storage circuit. The second drive strength may be less than the first drive strength. Access transistors with asymmetric drive strengths may be used to improve memory read/write performance.

Abstract: Integrated circuits may have arrays of memory elements. Data may be loaded into the memory elements and read from the memory elements using data lines. Address lines may be used to apply address signals to write address transistors and read circuitry. A memory element may include a bistable storage element. Read circuitry may be coupled between the bistable storage element and a data line. The read circuitry may include a data storage node. A capacitor may be coupled between the data storage node and ground and may be used in storing preloaded data from the bistable storage element. The read circuitry may include a transistor that is coupled between the bistable storage element and the data storage node and a transistor that is coupled between the data storage node and the data line.