Abstract: System and method for identifying nodes with packet loss in a wireless communication network. The method comprises a central probe server—establishing a TWAMP session with a plurality of nodes. The central probe server probes the plurality of nodes for packet loss for a time duration ?T and categorizes each of the plurality of nodes as one of violator node and non-violator node. A sectionalisation module retrieves a topology of the at least one violator node. The central probe server probes at least one neighboring node of the at least one violator node for packet loss for the time duration ?T. The sectionalisation module identifies the at least one violator node as one of a silo node and a daisy chain node based on the probe of the at least one neighboring node.

Abstract: System and method for identifying nodes with packet loss in a wireless communication network. The method comprises a central probe server—establishing a TWAMP session with a plurality of nodes. The central probe server probes the plurality of nodes for packet loss for a time duration ?T and categorizes each of the plurality of nodes as one of violator node and non-violator node. A sectionalisation module retrieves a topology of the at least one violator node. The central probe server probes at least one neighboring node of the at least one violator node for packet loss for the time duration ?T. The sectionalisation module identifies the at least one violator node as one of a silo node and a daisy chain node based on the probe of the at least one neighboring node.

Abstract: A multi play single fiber system is described. The system comprises a single fibre for provisioning one or more of Global System of Mobile (GSM) Communication, Code Division Multiple Access (CDMA), Worldwide Interoperability for Microwave Access (Wimax), Global Positioning System (GPS) based services implemented on one or more of: Asynchronous Transfer Mode (ATM), Time-Division Multiplexing (TDM), Transmission Control Protocol-Internet Protocol (TCP-IP), Radio Frequency (RF), Wavelength Division Multiplexing (WDM) or Dense Wavelength Division Multiplexing (SWDM) and a hardware coupled computer programmable device coupled with the single fiber to create plurality of tunnels within the said single fiber and create plurality of circuits within the said tunnels.

Abstract: In one form, a computer system includes a system processor operable to process data. The system includes a number of memory array chips coupled to the system processor by a system bus. Such a memory array chip includes random access memory partitioned into rows, each row having a number of memory words. The random access memory has an internal buffer and the buffer is operable to hold a plurality of the memory words. Such a memory array chip includes an embedded processor and an internal bus coupling the embedded processor to the internal buffer. The internal bus is capable of concurrently transferring the plurality of memory words of the internal buffer for processing by the embedded processor.

Abstract: A method and system for detecting a failure in a dynamic random access memory (DRAM) array having a plurality of cells organized in a matrix fashion of rows and columns. The method includes reading the content of a first row of cells of the memory array during a first refresh cycle. After obtaining the content from the first row of cells, a first complement of the content is generated. The generated first complement is then written back to the first row of cells during the writeback operation of the first refresh cycle. During the subsequent refresh cycle, the first complement in the first row of cells is read and a second complement of the first complement is generated. Next, the original content in the first row of cells is compared with the second complement. In response to the original content not being equal to the second complement, a control signal is generated to indicate a failure in the memory array.

Abstract: A fault tolerant memory system and method of operation thereof. The fault tolerant memory system includes a number of memory arrays including at least one spare memory array, wherein each of the memory arrays has an internal error detection circuit. In an advantageous embodiment, the internal error detection circuit includes an inverter, a register coupled to the inverter and a comparator for comparing the contents of the inverter and register. The comparator will generate an error signal to indicate a failed memory array in response to the contents of the inverter and register not being equal. The fault tolerant memory system also includes data correction logic that corrects data stored in a failed memory array and, in an advantageous embodiment, restores “corrupted” data in a failed array by reading the content of a row of cells in the failed memory array and generating a first complement of the content.

Abstract: A method for providing a fault tolerant memory system having a number of memory arrays that includes at least one spare memory array and utilizing a data word organization of greater than 4 bits. The method includes detecting a multi-bit word error in a memory array. In an advantageous embodiment, a single package detect (SPD) logic, for detecting a package error of 1-4 bits, is utilized to identify the failed memory array. Next, the content of a first row of cells in the failed memory array is read and a first complement of the content is generated. Subsequently, the first complement is written back to the first row of cells in the failed array. A second read operation is then initiated to retrieve the first complement from the failed memory array, following which, a second complement of the first complement is generated. The second complement is then written to a corresponding first row of cells in the spare memory array and the method is repeated for all row of cells in the failed memory array.

Abstract: A memory array system is provided comprising a plurality of rows of memory cells, each row having an address, wherein each memory cell stores volatile data requiring periodic refreshing. A refresh controller controls the periodic refreshing of data in each row of memory cells. A refresh address counter indicates the address of the row of cells for refreshing. A temporary data storer is used for storing data from the memory cell indicated for refreshing. A data inverter inverts data from the memory cell indicated for refreshing. A comparator associated with the temporary data storer and the data inverter compares data in those devices. An indicator bit is associated with the refresh address counter to indicate whether the data stored in the address indicated by the refresh address counter is inverted.

Abstract: In one form, a computer system includes a system processor operable to process data. The system includes a number of memory array chips coupled to the system processor by a system bus. Such a memory array chip includes random access memory partitioned into rows, each row having a number of memory words. The random access memory has an internal buffer and the buffer is operable to hold a plurality of the memory words. Such a memory array chip includes an embedded processor and an internal bus coupling the embedded processor to the internal buffer. The internal bus is capable of concurrently transferring the plurality of memory words of the internal buffer for processing by the embedded processor.

Abstract: A memory array system is provided comprising a plurality of rows of memory cells, each row having an address, wherein each memory cell stores volatile data requiring periodic refreshing. A refresh controller controls the periodic refreshing of data in each row of memory cells. A refresh address counter indicates the address of the row of cells for refreshing. A temporary data storer is used for storing data from the memory cell indicated for refreshing. A data inverter inverts data from the memory cell indicated for refreshing. A comparator associated with the temporary data storer and the data inverter compares data in those devices. An indicator bit is associated with the refresh address counter to indicate whether the data stored in the address indicated by the refresh address counter is inverted.

Abstract: The present invention provides an improved method and apparatus for performing decimal arithmetic using conventional parallel binary adders. In a first aspect of the present invention, a method for implementing decimal arithmetic using a radix (base) 100 and a method for implementing radix 1000 numbering system are disclosed. The first aspect of the present invention implements decimal arithmetic utilizing radix 100, where one-hundred decimal numbers, 0 through 99, are represented using seven BCD bits. In a second aspect of the present invention, a specialized high-speed radix 100 parallel adder is disclosed.

Abstract: A system and method for organizing compressed data on a storage disk to increase storage density. The method and system include a compressor for compressing a data block into a compressed data block, wherein N represents a compression ratio. The storage disk includes a first storage partition having N slots for storing compressed data, and a second storage partition also having N slots for storing overflow data. Each of the N slots in the first partition includes at least one address pointer for pointing to locations in the second partition. According to a further aspect of the system and method, if the compressed data block is less than or equal to 1/N of the data block size, then the compressed data block is stored in a first slot in the first storage partition.

Abstract: A system and method for organizing compressed data and uncompressed data in a storage system. The method and system include a compressor for compressing a data block into a compressed data block, wherein N represents a compression ratio. The storage disk includes a first disk partition having N slots for storing compressed data, and a second disk partition for storing uncompressed data. A portion of the N slots in the first partition include address pointers for pointing to locations in the second disk partition containing the uncompressed data.

Abstract: Aspects for caching storage data include partitioning a storage cache to include a compressed data partition and an uncompressed data partition, and adjusting a size of the compressed data partition and the uncompressed data partition for chosen performance characteristics. A data caching system aspect in a data processing system having a host system in communication with a storage system includes at least one storage device and at least one partially compressed cache. The at least one partially compressed cache further includes an uncompressed partition and a compressed partition, where the compressed partition stores at least a victim data unit from the uncompressed partition.

Abstract: Aspects for caching storage data include partitioning a storage cache to include a compressed data partition and an uncompressed data partition, and adjusting a size of the compressed data partition and the uncompressed data partition for chosen performance characteristics. A data caching system aspect in a data processing system having a host system in communication with a storage system includes at least one storage device and at least one partially compressed cache. The at least one partially compressed cache further includes an uncompressed partition and a compressed partition, where the compressed partition stores at least a victim data unit from the uncompressed partition.

Abstract: A method and apparatus for managing update writing in place in linear address space mapped memories. This is attained by partitioning the memory into compressed and uncompressed areas, estimating the percent of compressible images of fixed-length symbol strings recordable into the image locations, revising the estimate upward or downward as a function of the persistency of runs of writes to one area or the other, and adjusting the relative number of locations in the areas proportionally to the revised estimate.

Abstract: A method and apparatus in which on-chip functions are checked and any detected anomalies are located within a nested time interval. An on-chip function is tested by (1) applying a predetermined data pattern to the function, (2) computing a linear block error detection code residue from any output from the function being tested, and (3) comparing the residue to a error code residue (signature) derived from the output of a copy of the same function with the same data pattern. In one embodiment, the code signature has been previously derived from an error-free copy of the function. Where the signature is supplied contemporaneously by another copy of the same function also being tested, the function copy is not presumed error free. In both cases, any mismatch between the on-chip code residue and the signature indicates error, erasure, or fault. By either recursive reprocessing or shortening the intervals between comparisons, the mismatch can be located within a nested time or sequence interval.

Abstract: A method and means for detecting and correcting anomalies in a RAM-based FPGA by comparing CRC residues over portions of the RAM-stored connection bitmap with prestored residues derived from uncorrupted copies of the same bitmap portions. A mismatch selectively invokes either error reporting to the chip only, error reporting and immediate verification testing of counterpart FPGA chip functions, or error reporting, parity-based correction of the words in error, reprogramming of the chip functions with the corrected words, and verification testing.

Abstract: Memory system for internally rearranging fields in database records. The memory is separated into modules, each module separately addressable. Each memory module is addressed by selectively modifying a supplied address, for example by the output from exclusive-OR gates, having inputs from the address supplied to the memory system and another inputs from address modification registers. The address modification registers are selectively set by the external utilization device to permit reading different rows in the memory modules. The data output columns from the memory modules can be rearranged using selector devices such as demultiplexors. Data can be masked by precluding certain selector control signals.

Abstract: A method and means in a stored, program-controlled machine to maintain an uninterrupted access and copying of simple parity-coded words of an initial program load (IPL) or other software from a read-only memory or a memory with limited rewrite capability in the presence of detectable errors, erasures, or faults. The method utilizes detected parity error in a word copied out from storage to modify the address register to seek the same word from a mirror address of an image copy of the IPL. The image copy is stored at a second range of consecutive memory address nonintersecting and symmetric with the address range of the original IPL. The IPL is then accessed in the second address range until either another parity error causes a switch back to the original IPL or the program terminates.