Abstract: A computer structure comprises a first silicon substrate in which is formed computer circuitry and analogue circuitry for supporting communications. A second silicon substrate comprises a plurality of distributed capacitance units, and is connected to the first substrate via a set of connectors arranged extending depth-wise of the structure. The second substrate has an outer surface on which are arranged a supply voltage connector terminal and a ground connector terminal for connecting the computer structure to a supply voltage for the analogue circuitry and to ground respectively. One or more of the distributed capacitance units of the second silicon substrate is connected between the supply voltage connector and the ground connector terminal via one or more of the set of connectors to provide a decoupling capacitor for the analogue circuitry.

Abstract: A method for defining an aligned logic cell grid and interconnect layout of a semiconductor integrated circuit having a logic cell is disclosed. The interconnect layout is resized in accordance with a highest common denominator of an initial routing pitch of the interconnect layout and a transistor pitch of the logic cell. The cell grid is aligned with the resized routing pitch which provides efficient routing density and transistor performance, minimizes excess transistor area and wire routing waste while maximizing cell packing density.

Abstract: A method (300) for optimising transistor performance in semiconductor integrated circuits built from standard cells (12), or custom transistor level layout, is disclosed. An active area of NMOS diffusion is extended with a joining area (102) between two adjacent cells (112) having the same net on diffusion at the adjacent edges of each cell. The diffusion area is extended to limit the occurrence of active and nonactive interface to minimise lattice strain effects and improve transistor performance.