Patents by Inventor Shantanu Chakrabartty
Shantanu Chakrabartty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10446234Abstract: A timer module including a timer and a compensation circuit coupled to the timer is provided. The timer measures time over a first monitoring period. The timer includes a floating-gate and an energy barrier. The floating-gate stores electrons and has an initial state and a measured state. The measured state includes a current time and a current floating-gate voltage. The energy barrier is positioned adjacent the floating-gate and leaks electrons from an ambient environment of the timer to the floating-gate at a predetermined leakage rate using Fowler-Nordheim (FN) tunneling. The compensation circuit selectably adjusts the first monitoring period to facilitate improved robustness of the timer with respect to fabrication mismatch due to the self-compensating dynamics of FN tunneling.Type: GrantFiled: October 24, 2017Date of Patent: October 15, 2019Assignee: Washington UniversityInventors: Shantanu Chakrabartty, Liang Zhou
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Publication number: 20190094078Abstract: A sensor system for detecting events is provided. The sensor system includes a sensor and a read-out interface. The sensor includes a transducer and a memory device. The transducer detects an event and generates a sensor signal in response to the event. The memory device includes a floating-gate with a sensing interface coupled to the transducer. The sensing interface has an energy barrier that leaks electrons at a predetermined electron leakage rate through Fowler-Nordheim (F-N) tunneling. The sensor signal alters a geometry of the energy barrier to change the electron leakage rate. The read-out interface is communicatively coupled to the memory device and retrieves data stored on the memory device for analysis. The event and a timestamp of the event are identifiable from the stored data.Type: ApplicationFiled: February 28, 2017Publication date: March 28, 2019Applicant: Washington UniversityInventors: Shantanu Chakrabartty, Liang Zhou
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Publication number: 20190000419Abstract: A sensor system includes a sensor module that is embedded in a target environment and a signal system. The sensor module includes an active sensor of a first type that detects a target element in the target environment and a reference sensor of the first type that prevents detection of target elements by the reference sensor. The active sensor and the reference sensor receive an ultrasonic signal and respectively generate a first response signal and a second response signal. The first response signal is at least partially as a function of the detected target element. The signal system includes an ultrasonic transducer that generates the ultrasonic signal and receives the first and second response signals, and a controller communicatively coupled to the ultrasonic transducer. The controller identifies the detected target element based at least partially on the first and second response signals.Type: ApplicationFiled: June 29, 2018Publication date: January 3, 2019Applicant: Washington UniversityInventors: Shantanu Chakrabartty, Yarub Alazzawi, Srikanth Signamaneni, Keng-Ku Liu, Mingquan Yuan
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Publication number: 20180114577Abstract: A timer module including a timer and a compensation circuit coupled to the timer is provided. The timer measures time over a first monitoring period. The timer includes a floating-gate and an energy barrier. The floating-gate stores electrons and has an initial state and a measured state. The measured state includes a current time and a current floating-gate voltage. The energy barrier is positioned adjacent the floating-gate and leaks electrons from an ambient environment of the timer to the floating-gate at a predetermined leakage rate using Fowler-Nordheim (FN) tunneling. The compensation circuit selectably adjusts the first monitoring period to facilitate improved robustness of the timer with respect to fabrication mismatch due to the self-compensating dynamics of FN tunneling.Type: ApplicationFiled: October 24, 2017Publication date: April 26, 2018Inventors: Shantanu Chakrabartty, Liang Zhou
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Publication number: 20180087957Abstract: A variance-based substrate computing system is disclosed. The variance-based computing system includes a sensor configured to be embedded in a structure, the sensor further configured to generate an electrical output signal in response to a mechanical input, and a processor configured to receive the electrical output signal. The processor includes a measurement module configured to determine a variance of the electrical output signal about a base value, and a transformation module configured to generate a binary output signal based upon the variance.Type: ApplicationFiled: September 28, 2017Publication date: March 29, 2018Inventors: Shantanu Chakrabartty, Sri Harsha Kondapalli, Xuan Zhang
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Patent number: 9793830Abstract: A self-powered sensing system is provided for the monitoring of quasi-static structural responses. The sensing system is comprised of: an energy concentrator having a member configured to detect a variation of a physical stimuli and change shape in response to the variation of the physical stimuli, where the variation typically occurs at a frequency less than one Hertz; a transducer coupled the member of the energy concentrator and generates a voltage in response to the change in shape of the member; and an event logging circuit configured to receive the voltage from the transducer and log the voltage in a non-volatile memory. Physical stimuli may include temperature, pressure or an applied force.Type: GrantFiled: September 16, 2014Date of Patent: October 17, 2017Assignee: Board of Trustees of Michigan State UniversityInventors: Nizar Lajnef, Shantanu Chakrabartty, Rigoberto Burgueno, Borchani Wassim
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Patent number: 9437602Abstract: A temperature compensation technique is provided for a non-volatile memory arrangement. The memory arrangement includes: a memory circuit (12) having a floating gate transistor (P3) operating in weak-inversion mode and a varactor (Cv) with a terminal electrically coupled to a gate node of the floating gate transistor; a first current reference circuit (14) having a floating gate transistor (PI); a second current reference circuit (16) having a floating gate transistor (P2); and a control module (18) configured to selectively receive a reference current (I1, I2) from a drain of the floating gate transistor in each of the first and second current reference circuits. The control module operates to determine a ratio between the reference currents received from the first and second current reference circuits, generate a tuning voltage (Vx) in accordance with the ratio between the reference currents and apply the tuning voltage to the varactor in the memory circuit.Type: GrantFiled: November 27, 2012Date of Patent: September 6, 2016Assignee: Board of Trustees of Michigan State UniversityInventors: Shantanu Chakrabartty, Ming Gu, Chenling Huang
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Publication number: 20160233797Abstract: A self-powered sensing system is provided for the monitoring of quasi-static structural responses. The sensing system is comprised of: an energy concentrator having a member configured to detect a variation of a physical stimuli and change shape in response to the variation of the physical stimuli, where the variation typically occurs at a frequency less than one Hertz; a transducer coupled the member of the energy concentrator and generates a voltage in response to the change in shape of the member; and an event logging circuit configured to receive the voltage from the transducer and log the voltage in a non-volatile memory. Physical stimuli may include temperature, pressure or an applied force.Type: ApplicationFiled: September 16, 2014Publication date: August 11, 2016Applicant: BOARD OF TRUSTEES OF MICHIGAN STATE UNIVERSITYInventors: Nizar LAJNEF, Shantanu CHAKRABARTTY, Rigoberto BURGUENO, Borchani WASSIM
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Patent number: 9331265Abstract: A linear hot-electron injection technique is provided for a non-volatile memory arrangement. The non-volatile memory is comprised of: a floating gate transistor; a capacitor with a first terminal electrically coupled to the gate node of the floating gate transistor; a current reference circuit electrically coupled to the source node of the floating gate transistor; and a feedback circuit electrically coupled between the source node of the floating gate transistor and a second terminal of the capacitor. The feedback circuit operates to adjust a voltage at the gate node of the floating gate transistor in accordance with a source-to-drain voltage across the floating gate transistor.Type: GrantFiled: January 28, 2013Date of Patent: May 3, 2016Assignee: Board of Trustees of Michigan State UniversityInventor: Shantanu Chakrabartty
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Patent number: 8963647Abstract: A method is provided for implementing a timer using a floating-gate transistor. The method includes: injecting a charge into a floating-gate transistor at an initial time, where a gate terminal of the floating-gate transistor is comprised of polysilicon encased by an insulating material; creating lattice imperfections at boundary of the polysilicon to cause leakage from the floating-gate transistor; measuring current read out from the floating-gate transistor at a time subsequent to the initial time; and determining an amount of time between the initial time and the subsequent time using the measured current.Type: GrantFiled: February 20, 2013Date of Patent: February 24, 2015Assignee: Board of Trustees of Michigan State UniversityInventor: Shantanu Chakrabartty
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Publication number: 20150027237Abstract: A linear hot-electron injection technique is provided for a non-volatile memory arrangement. The non-volatile memory is comprised of: a floating gate transistor; a capacitor with a first terminal electrically coupled to the gate node of the floating gate transistor; a current reference circuit electrically coupled to the source node of the floating gate transistor; and a feedback circuit electrically coupled between the source node of the floating gate transistor and a second terminal of the capacitor. The feedback circuit operates to adjust a voltage at the gate node of the floating gate transistor in accordance with a source-to-drain voltage across the floating gate transistor.Type: ApplicationFiled: January 28, 2013Publication date: January 29, 2015Applicant: Board of Trustees of Michigan State UniversityInventor: Shantanu Chakrabartty
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Publication number: 20150008496Abstract: A temperature compensation technique is provided for a non-volatile memory arrangement. The memory arrangement includes: a memory circuit (12) having a floating gate transistor (P3) operating in weak-inversion mode and a varactor (Cv) with a terminal electrically coupled to a gate node of the floating gate transistor; a first current reference circuit (14) having a floating gate transistor (PI); a second current reference circuit (16) having a floating gate transistor (P2); and a control module (18) configured to selectively receive a reference current (I1, I2) from a drain of the floating gate transistor in each of the first and second current reference circuits. The control module operates to determine a ratio between the reference currents received from the first and second current reference circuits, generate a tuning voltage (Vx) in accordance with the ratio between the reference currents and apply the tuning voltage to the varactor in the memory circuit.Type: ApplicationFiled: November 27, 2012Publication date: January 8, 2015Applicant: Board of Trustees of Michigan State UniversityInventors: Shantanu Chakrabartty, Ming Gu, Chenling Huang
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Publication number: 20140232444Abstract: A method is provided for implementing a timer using a floating-gate transistor. The method includes: injecting a charge into a floating-gate transistor at an initial time, where a gate terminal of the floating-gate transistor is comprised of polysilicon encased by an insulating material; creating lattice imperfections at boundary of the polysilicon to cause leakage from the floating-gate transistor; measuring current read out from the floating-gate transistor at a time subsequent to the initial time; and determining an amount of time between the initial time and the subsequent time using the measured current.Type: ApplicationFiled: February 20, 2013Publication date: August 21, 2014Applicant: BOARD OF TRUSTEES OF MICHIGAN STATE UNIVERSITYInventor: Shantanu Chakrabartty
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Publication number: 20130297299Abstract: The speech feature extraction algorithm is based on a hierarchical combination of auditory similarity and pooling functions. Computationally efficient features referred to as “Sparse Auditory Reproducing Kernel” (SPARK) coefficients are extracted under the hypothesis that the noise-robust information in speech signal is embedded in a reproducing kernel Hilbert space (RKHS) spanned by overcomplete, nonlinear, and time-shifted gammatone basis functions. The feature extraction algorithm first involves computing kernel based similarity between the speech signal and the time-shifted gammatone functions, followed by feature pruning using a simple pooling technique (“MAX” operation). Different hyper-parameters and kernel functions may be used to enhance the performance of a SPARK based speech recognizer.Type: ApplicationFiled: March 7, 2013Publication date: November 7, 2013Applicant: Board of Trustees of Michigan State UniversityInventors: Shantanu Chakrabartty, Amin Fazeldehkordi
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Patent number: 8060810Abstract: A margin decoding communications system includes a circuit receiving a message encoded by an iterative code and processing the message into scores. A normalization process module receives the scores and iteratively approximates log-map normalization factors of the scores to generate approximation normalization factors. An element receives the message and the approximation normalization factors and decodes the received message based on the approximation normalization factors.Type: GrantFiled: April 6, 2007Date of Patent: November 15, 2011Assignee: Board of Trustees of Michigan State UniversityInventor: Shantanu Chakrabartty
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Patent number: 8056420Abstract: A self-powered sensor is provided for fatigue monitoring and other low power requirement applications. The self-powered sensor is comprised of: a piezoelectric transducer; a non-volatile memory comprised of at least one floating gate transistor; and a current reference circuit adapted to receive a voltage signal from the piezoelectric transducer and operable to output an injection current into the non-volatile memory. The current reference circuit may employ a floating gate transistor operating in a weak-inversion mode.Type: GrantFiled: August 24, 2007Date of Patent: November 15, 2011Assignee: Board of Trustees of Michigan State UniversityInventors: Shantanu Chakrabartty, Nizar Lajnef, Niell G. Elvin, Amit S. Gore
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Patent number: 7757565Abstract: A self-powered sensor is provided for strain-rate monitoring and other low power requirement applications. The self-powered sensor is comprised of: a piezoelectric transducer; a non-volatile memory comprised of at least one floating gate transistor; a current reference circuit adapted to receive a voltage signal from the piezoelectric transducer and operable to output a reference current into the non-volatile memory; an impact-monitoring circuit having a triggering circuit and a switch; the triggering circuit adapted to receive the voltage signal from the piezoelectric transducer and operable to control the switch based on the rate of change of the voltage signal.Type: GrantFiled: November 19, 2008Date of Patent: July 20, 2010Assignee: Board of Trustees Operating Michigan State UniversityInventor: Shantanu Chakrabartty
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Publication number: 20090120200Abstract: A self-powered sensor is provided for strain-rate monitoring and other low power requirement applications. The self-powered sensor is comprised of: a piezoelectric transducer; a non-volatile memory comprised of at least one floating gate transistor; a current reference circuit adapted to receive a voltage signal from the piezoelectric transducer and operable to output a reference current into the non-volatile memory; an impact-monitoring circuit having a triggering circuit and a switch; the triggering circuit adapted to receive the voltage signal from the piezoelectric transducer and operable to control the switch based on the rate of change of the voltage signal.Type: ApplicationFiled: November 19, 2008Publication date: May 14, 2009Applicant: Board of Trustees of Michigan State UniversityInventor: Shantanu Chakrabartty
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Patent number: 7479911Abstract: A method is provided for multi-channel analog-to-digital conversion. The method includes: receiving an input vector which represents a plurality of analog signals; transforming the input vector using a linear transformation matrix; converting the transformed input vector to a digital stream using an array of sigma-delta converter; and adapting the linear transform matrix to maximize de-correlation between the signals represented in the input vector.Type: GrantFiled: August 24, 2007Date of Patent: January 20, 2009Assignee: Board of Trustees of Michigan State UniversityInventor: Shantanu Chakrabartty
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Publication number: 20080055133Abstract: A method is provided for multi-channel analog-to-digital conversion. The method includes: receiving an input vector which represents a plurality of analog signals; transforming the input vector using a linear transformation matrix; converting the transformed input vector to a digital stream using an array of sigma-delta converter; and adapting the linear transform matrix to maximize de-correlation between the signals represented in the input vector.Type: ApplicationFiled: August 24, 2007Publication date: March 6, 2008Applicant: Board of Trustees of Michigan State UniversityInventor: Shantanu Chakrabartty