Patents by Inventor Shantanu Ganguly

Shantanu Ganguly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8934314
    Abstract: Embodiments of an apparatus and method to improve power delivery including a pre-charge circuit that may include a first voltage supply rail configured to provide a first voltage amount to perform a first phase of a pre-charge of a bit line and a second voltage supply rail configured to provide a second voltage amount to perform a second phase of the pre-charge of the bit line are described herein. In embodiments, the pre-charge circuit may be a pre charge circuit for a static random-access memory (SRAM) memory cell.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: January 13, 2015
    Assignee: Intel Corporation
    Inventors: Mohammed H. Taufique, Daniel J. Cummings, Hieu T. Ngo, Shantanu Ganguly
  • Publication number: 20140010000
    Abstract: Embodiments of an apparatus and method to improve power delivery including a pre-charge circuit that may include a first voltage supply rail configured to provide a first voltage amount to perform a first phase of a pre-charge of a bit line and a second voltage supply rail configured to provide a second voltage amount to perform a second phase of the pre-charge of the bit line are described herein. In embodiments, the pre-charge circuit may be a pre charge circuit for a static random-access memory (SRAM) memory cell.
    Type: Application
    Filed: December 28, 2011
    Publication date: January 9, 2014
    Inventors: Mohammed H. Taufique, Daniel J. Cummings, Hieu T. Ngo, Shantanu Ganguly
  • Patent number: 7137097
    Abstract: A method, system, computer system, and computer program product including an algorithm that performs the constraints-based global routing step in the physical design of integrated circuits. The algorithm is based on finding routes for the entire circuit based on constraints being satisfied for the entire design. Initially, for each net, a set of possible routing solutions is determined based on applicable constraints. The possible solutions for the nets are combined to create a highly-connected “intersection graph,” with each intersection graph node representing a net. The intersection graph is partitioned based on constraints and performance criteria. An optimal solution is determined for each partition. The optimal solutions for the partitions are then combined to produce a global routing solution. The global routing solution is provided to a detailed router, which completes the routing for the design.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: November 14, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Sandeep A. Aji, Ankur Narang, Shantanu Ganguly
  • Publication number: 20040044979
    Abstract: A method, system, computer system, and computer program product including an algorithm that performs the constraints-based global routing step in the physical design of integrated circuits. The algorithm is based on finding routes for the entire circuit based on constraints being satisfied for the entire design. Initially, for each net, a set of possible routing solutions is determined based on applicable constraints. The possible solutions for the nets are combined to create a highly-connected “intersection graph,” with each intersection graph node representing a net. The intersection graph is partitioned based on constraints and performance criteria. An optimal solution is determined for each partition. The optimal solutions for the partitions are then combined to produce a global routing solution. The global routing solution is provided to a detailed router, which completes the routing for the design.
    Type: Application
    Filed: August 27, 2002
    Publication date: March 4, 2004
    Inventors: Sandeep A. Aji, Ankur Narang, Shantanu Ganguly
  • Patent number: 6480996
    Abstract: An automatic and parameterized compute implemented method for transposing wires in an integrated circuit design can y bus lines with similar impedances, and therefore similar signal transmission characteristics. Using a specially designed CAD tool, a user can specify a transposing porn, intervals at which to transpose wires, and a metal layer through which to accomplish the transposing in the integrated circuit. Using a routing database the tool then automatically determines the locations in the design where transposing needs to be performed, re-routes the wires being transposed while optimizing the circuit design space being used, and re-routes (or causes the re-route of) any other wires affected by the transposing process. The result is a new version of the routing database reflecting transposition, but with no change to the circuit's netlist.
    Type: Grant
    Filed: July 6, 2000
    Date of Patent: November 12, 2002
    Assignee: Sun Microsystems, Inc.
    Inventors: Sandeep A. Aji, Shantanu Ganguly, John Paz