Patents by Inventor Shantanu R. Rajwade
Shantanu R. Rajwade has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190304543Abstract: In one embodiment, an apparatus comprises a memory comprising a first group of memory cells, a second group of memory cells, and a controller to program one or more lower pages of data to the first group of memory cells; store dynamic start voltage information, the dynamic start voltage information indicative of a rate of programming of at least a portion of the first group of memory cells; determine a start program voltage based on the dynamic start voltage information; and apply the start program voltage to the second group of memory cells during a first program pass of a program operation, the program operation to program one or more lower pages of data to the second group of memory cells.Type: ApplicationFiled: March 4, 2019Publication date: October 3, 2019Applicant: Intel CorporationInventors: Purval Shyam Sule, Aliasgar S. Madraswala, Shantanu R. Rajwade, Trupti Ramkrishna Bemalkhedkar, Leonard Aaron Turcios, Kristopher H. Gaewsky
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Patent number: 10430114Abstract: Apparatuses and methods for performing buffer operations in memory are provided. A method can include storing second page data and third page data on a buffer while programming first page data during a first pass programming operation and programming the second page data and the third page data from the buffer to the array of memory cells during a second pass programming operation.Type: GrantFiled: March 29, 2018Date of Patent: October 1, 2019Assignee: Micron Technology, Inc.Inventors: Pranav Kalavade, Shantanu R. Rajwade
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Publication number: 20190258404Abstract: Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.Type: ApplicationFiled: May 1, 2019Publication date: August 22, 2019Inventors: Shantanu R. Rajwade, Pranav Kalavade, Toru Tanzawa
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Patent number: 10379738Abstract: Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.Type: GrantFiled: December 26, 2017Date of Patent: August 13, 2019Assignee: Micron Technology, Inc.Inventors: Shantanu R. Rajwade, Pranav Kalavade, Toru Tanzawa
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Patent number: 10289313Abstract: In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory. The storage device is to receive a read request from a computing host; identify a plurality of pages specified by the read request that are stored in the same group of memory cells of the NAND flash memory, wherein each memory cell of the group of memory cells is to store a bit of each of the plurality of identified pages; and read, in a single read cycle, the plurality of pages from the group of memory cells of the NAND flash memory.Type: GrantFiled: June 28, 2016Date of Patent: May 14, 2019Assignee: Intel CorporationInventors: Han Liu, Shantanu R. Rajwade, Pranav Kalavade
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Patent number: 10224107Abstract: In one embodiment, an apparatus comprises a memory comprising a first group of memory cells, a second group of memory cells, and a controller to program one or more lower pages of data to the first group of memory cells; store dynamic start voltage information, the dynamic start voltage information indicative of a rate of programming of at least a portion of the first group of memory cells; determine a start program voltage based on the dynamic start voltage information; and apply the start program voltage to the second group of memory cells during a first program pass of a program operation, the program operation to program one or more lower pages of data to the second group of memory cells.Type: GrantFiled: September 29, 2017Date of Patent: March 5, 2019Assignee: Intel CorporationInventors: Purval Shyam Sule, Aliasgar S. Madraswala, Shantanu R. Rajwade, Trupti Ramkrishna Bemalkhedkar, Leonard Aaron Turcios, Kristopher H. Gaewsky
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Publication number: 20190006016Abstract: A programming of a memory device configurable to reach a plurality of voltage levels is initiated. For each voltage level to be reached, a checkpoint is set up within a sequence of program pulses applied for the programming of the memory device, to determine whether a plurality of memory cells of the memory device have reached the voltage level. The programming of the memory device is aborted, in response to determining at the checkpoint that the plurality of memory cells have not reached the voltage level.Type: ApplicationFiled: June 29, 2017Publication date: January 3, 2019Inventors: Ali KHAKIFIROOZ, Pranav KALAVADE, Shantanu R. RAJWADE, Aliasgar S. MADRASWALA, Uday CHANDRASEKHAR, Purval S. SULE, Sagar UPADHYAY
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Patent number: 10141071Abstract: Methods and apparatus related to predictive Count Fail Byte (CFBYTE) for non-volatile memory are described. In one embodiment, logic determines a number of memory cells of the non-volatile memory that would pass or fail verification in a current program loop. The logic determines the number of the memory cells based at least in part on information from a previous program loop. The previous program loop is executed prior to the current program loop. The logic causes inhibition of one or more verification pulses to be issued in the current program loop based on comparison of the information from the previous program loop and a threshold value. Other embodiments are also disclosed and claimed.Type: GrantFiled: December 26, 2015Date of Patent: November 27, 2018Assignee: Intel CorporationInventors: Shantanu R. Rajwade, Pranav Kalavade
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Publication number: 20180217782Abstract: Apparatuses and methods for performing buffer operations in memory are provided. One example method can include storing second page data and third page data on a buffer while programming first page data during a first pass programming operation and programming the second page data and the third page data from the buffer to the array of memory cells during a second pass programming operation.Type: ApplicationFiled: March 29, 2018Publication date: August 2, 2018Inventors: Pranav Kalavade, Shantanu R. Rajwade
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Publication number: 20180143784Abstract: Apparatuses and methods for performing buffer operations in memory are provided. One example method can include storing second page data and third page data on a buffer while programming first page data during a first pass programming operation and programming the second page data and the third page data from the buffer to the array of memory cells during a second pass programming operation.Type: ApplicationFiled: November 22, 2016Publication date: May 24, 2018Inventors: Pranav Kalavade, Shantanu R. Rajwade
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Patent number: 9977622Abstract: Apparatuses and methods for performing buffer operations in memory are provided. One example method can include storing second page data and third page data on a buffer while programming first page data during a first pass programming operation and programming the second page data and the third page data from the buffer to the array of memory cells during a second pass programming operation.Type: GrantFiled: November 22, 2016Date of Patent: May 22, 2018Assignee: Micron Technology, Inc.Inventors: Pranav Kalavade, Shantanu R. Rajwade
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Publication number: 20180136845Abstract: Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.Type: ApplicationFiled: December 26, 2017Publication date: May 17, 2018Applicant: Micron Technology, Inc.Inventors: Shantanu R. Rajwade, Pranav Kalavade, Toru Tanzawa
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Publication number: 20180122487Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.Type: ApplicationFiled: September 26, 2017Publication date: May 3, 2018Inventors: Shantanu R. RAJWADE, Pranav KALAVADE, Neal R. MIELKE, Krishna K. PARAT, Shyam Sunder RAGHUNATHAN
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Patent number: 9910594Abstract: Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.Type: GrantFiled: November 5, 2015Date of Patent: March 6, 2018Assignee: Micron Technology, Inc.Inventors: Shantanu R. Rajwade, Pranav Kalavade, Toru Tanzawa
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Patent number: 9865357Abstract: Technology for performing read operations in a memory device or system is described. The device or system can include an array of memory cells. The device or system can include a first decode circuit, and can further include a second decode circuit. The device or system can include a voltage regulator configured to perform a read operation by providing, based on one or more signals received from at least one of the first decode circuit or the second decode circuit, a voltage to a selected plane or a selected sub-plane in the array of memory cells.Type: GrantFiled: December 30, 2016Date of Patent: January 9, 2018Assignee: Intel CorporationInventors: Deepak Thimmegowda, Pranav Kalavade, Aaron Yip, Shantanu R. Rajwade
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Publication number: 20170371565Abstract: In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory. The storage device is to receive a read request from a computing host; identify a plurality of pages specified by the read request that are stored in the same group of memory cells of the NAND flash memory, wherein each memory cell of the group of memory cells is to store a bit of each of the plurality of identified pages; and read, in a single read cycle, the plurality of pages from the group of memory cells of the NAND flash memory.Type: ApplicationFiled: June 28, 2016Publication date: December 28, 2017Applicant: Intel CorporationInventors: Han Liu, Shantanu R. Rajwade, Pranav Kalavade
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Publication number: 20170371779Abstract: In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory. The storage device is to receive a write request from a computing host, the write request to specify data to be written to the NAND flash memory; perform a number of program loops to program the data into a plurality of cells of the NAND flash memory, wherein a program loop comprises application of a program voltage to a wordline of the memory to change the threshold voltage of at least one cell of the plurality of cells; and wherein the number of program loops is to be determined prior to receipt of the write request and based on a distribution of threshold voltages of the cells or determined based on tracking a number of program errors for only a portion of the plurality of cells.Type: ApplicationFiled: June 28, 2016Publication date: December 28, 2017Applicant: Intel CorporationInventors: Shantanu R. Rajwade, Andrea D'alessandro, Pranav Kalavade, Violante Moschiano
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Patent number: 9852065Abstract: In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory. The storage device is to receive a write request from a computing host, the write request to specify data to be written to the NAND flash memory; perform a number of program loops to program the data into a plurality of cells of the NAND flash memory, wherein a program loop comprises application of a program voltage to a wordline of the memory to change the threshold voltage of at least one cell of the plurality of cells; and wherein the number of program loops is to be determined prior to receipt of the write request and based on a distribution of threshold voltages of the cells or determined based on tracking a number of program errors for only a portion of the plurality of cells.Type: GrantFiled: June 28, 2016Date of Patent: December 26, 2017Assignee: Intel CorporationInventors: Shantanu R. Rajwade, Andrea D'alessandro, Pranav Kalavade, Violante Moschiano
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Patent number: 9792997Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.Type: GrantFiled: June 15, 2016Date of Patent: October 17, 2017Assignee: Intel CorporationInventors: Shantanu R. Rajwade, Pranav Kalavade, Neal R. Mielke, Krishna K. Parat, Shyam Sunder Raghunathan
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Patent number: 9703494Abstract: In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory. The storage device is to store a first page of data in a plurality of cells of the NAND flash memory in a first programming pass; and preserve the readability of the first page of data in the plurality of cells during a subsequent programming pass comprising a plurality of program loops, at least one of the plurality of program loops to comprise application of a first voltage to a first group of cells of the plurality of cells and application of a second voltage to a second group of cells of the plurality of cells, wherein the first group comprises cells that were not programmed in the first programming pass and the second group comprises cells that were programmed in the first programming pass.Type: GrantFiled: September 26, 2016Date of Patent: July 11, 2017Assignee: Intel CorporationInventors: Shantanu R. Rajwade, Pranav Kalavade