Patents by Inventor Shantanu Rajwade
Shantanu Rajwade has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240013840Abstract: Memories having a controller configured to perform methods during programming operations including apply a first voltage level to a data line selectively connected to a selected memory cell selected, apply a lower second voltage level to a select gate connected between the data line and the memory cell, decrease the voltage level applied to the data line from the first voltage level to a third voltage level while continuing to apply the second voltage level to the select gate, increase the voltage level applied to the select gate from the second voltage level to a fourth voltage level after the voltage level of the data line settles to the third voltage level, and apply a programming voltage to the memory cell after increasing the voltage level applied to the select gate to the fourth voltage level.Type: ApplicationFiled: July 21, 2023Publication date: January 11, 2024Inventors: Violante Moschiano, Purval S. Sule, Han Liu, Andrea D'alessandro, Pranav Kalavade, Han Zhao, Shantanu Rajwade
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Publication number: 20230352092Abstract: Systems, apparatuses and methods may provide for technology that issues a program pulse to a selected subblock of a NAND memory array, conducts a pulse recovery phase after the program pulse, and shuts down unselected subblocks in the NAND memory array during the pulse recovery phase.Type: ApplicationFiled: April 28, 2022Publication date: November 2, 2023Inventors: Tarek Ameen, Shantanu Rajwade, Hsiao Yu Chang, Rohit Shenoy, Pranav Chava, Xin Sun, Pratyush Chandrapati
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Publication number: 20230317144Abstract: An embodiment of an apparatus may include NAND memory organized as two or more memory planes and a controller communicatively coupled to the NAND memory, the controller including circuitry to provide synchronous independent plane read operations for the two or more memory planes of the NAND memory. Other embodiments are disclosed and claimed.Type: ApplicationFiled: March 29, 2022Publication date: October 5, 2023Applicant: Intel NDTM US LLCInventors: Chang Wan Ha, Binh Ngo, Ali Khakifirooz, Aliasgar S. Madraswala, Bharat Pathak, Pranav Kalavade, Shantanu Rajwade
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Patent number: 11721396Abstract: Memories having a controller configured to perform methods during programming operations including apply a first voltage level to a data line selectively connected to a selected memory cell selected, apply a lower second voltage level to a select gate connected between the data line and the memory cell, decrease the voltage level applied to the data line from the first voltage level to a third voltage level while continuing to apply the second voltage level to the select gate, increase the voltage level applied to the select gate from the second voltage level to a fourth voltage level after the voltage level of the data line settles to the third voltage level, and apply a programming voltage to the memory cell after increasing the voltage level applied to the select gate to the fourth voltage level.Type: GrantFiled: September 4, 2020Date of Patent: August 8, 2023Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Purval S. Sule, Han Liu, Andrea D'Alessandro, Pranav Kalavade, Han Zhao, Shantanu Rajwade
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Publication number: 20230061293Abstract: Systems, apparatuses and methods may provide for technology that conducts a pulse-verify loop sequence from a first program level in targeted NAND memory cells to a next-to-last program level in the memory cells, wherein the pulse-verify loop sequence includes an issuance of a program pulse and one or more verify pulses to the memory cells on a per program level basis, and wherein successive program pulses differ from one another by a gate step voltage amount. The technology may also issue a last level program pulse to the memory cells at a last program level, issue a single verify pulse to the memory cells after the last level program pulse, and issue a gate step pulse to the memory cells at a variable program level, wherein the variable program level differs from the last program level by an amount that is greater than the gate step voltage amount.Type: ApplicationFiled: August 25, 2021Publication date: March 2, 2023Inventors: Sagar Upadhyay, Archana Tankasala, Aliasgar S. Madraswala, Shantanu Rajwade
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Publication number: 20230044991Abstract: Systems, apparatuses and methods may provide for technology that detects a request to program a NAND memory containing a plurality of dies and programs the NAND memory on a stripe-by-stripe basis, wherein each stripe spans the plurality of dies and includes multiple types of pages. The multiple types of pages may reduce program time variability across the stripes and reduce the error susceptibility of the NAND memory.Type: ApplicationFiled: August 4, 2021Publication date: February 9, 2023Inventors: Shantanu Rajwade, Kartik Ganapathi, Rohit Shenoy, Kristopher Gaewsky, MarkAnthony Golez, Vivek Angoth, Pranav Kalavade, Sarvesh Gangadhar
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Publication number: 20220310160Abstract: Systems, apparatuses and methods may provide for technology that boosts strings of a plurality of NAND sub-blocks to a pass voltage, deboosts a first subset of the boosted strings based on data associated with the plurality of NAND sub-blocks, and simultaneously programs the first subset while a second subset of the boosted strings remain at the pass voltage. In one example, to boost the strings of the NAND sub-blocks, the technology applies the pass voltage to selected and unselected wordlines that are connected to the NAND sub-blocks while selected and unselected strings are disconnected from a bitline that receives the data associated with the NAND sub-blocks.Type: ApplicationFiled: March 25, 2021Publication date: September 29, 2022Inventors: Ali Khakifirooz, Pranav Kalavade, Shantanu Rajwade, Tarek Ahmed Ameen Beshari
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Publication number: 20210257036Abstract: Techniques and mechanisms for verifying the programming of a multi-bit cell of a memory array. In an embodiment, program verification is performed based on a signal, other than a word line voltage, which includes an indication of a reference voltage that is to be a basis for evaluating a currently programmed threshold voltage of a memory cell. A determination that the particular indication is to be communicated with the signal is made based on a detected state of the memory device which includes the memory cell. In another embodiment, the detected state includes one of a thermal condition at the memory array, a pressure condition at the memory array, a wear condition of the memory array, or a relative position of the cell with respect to one or more other cells of the memory array.Type: ApplicationFiled: February 13, 2020Publication date: August 19, 2021Applicant: Intel CorporationInventors: Xiang Yang, Tarek Ahmed Ameen Beshari, Narayanan Ramanan, Arun Thathachary, Shantanu Rajwade, Matin Amani
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Patent number: 11094386Abstract: Techniques and mechanisms for verifying the programming of a multi-bit cell of a memory array. In an embodiment, program verification is performed based on a signal, other than a word line voltage, which includes an indication of a reference voltage that is to be a basis for evaluating a currently programmed threshold voltage of a memory cell. A determination that the particular indication is to be communicated with the signal is made based on a detected state of the memory device which includes the memory cell. In another embodiment, the detected state includes one of a thermal condition at the memory array, a pressure condition at the memory array, a wear condition of the memory array, or a relative position of the cell with respect to one or more other cells of the memory array.Type: GrantFiled: February 13, 2020Date of Patent: August 17, 2021Assignee: Intel CorporationInventors: Xiang Yang, Tarek Ahmed Ameen Beshari, Narayanan Ramanan, Arun Thathachary, Shantanu Rajwade, Matin Amani
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Publication number: 20200402586Abstract: Memories having a controller configured to perform methods during programming operations including apply a first voltage level to a data line selectively connected to a selected memory cell selected, apply a lower second voltage level to a select gate connected between the data line and the memory cell, decrease the voltage level applied to the data line from the first voltage level to a third voltage level while continuing to apply the second voltage level to the select gate, increase the voltage level applied to the select gate from the second voltage level to a fourth voltage level after the voltage level of the data line settles to the third voltage level, and apply a programming voltage to the memory cell after increasing the voltage level applied to the select gate to the fourth voltage level.Type: ApplicationFiled: September 4, 2020Publication date: December 24, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Violante Moschiano, Purval S. Sule, Han Liu, Andrea D'Alessandro, Pranav Kalavade, Han Zhao, Shantanu Rajwade
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Patent number: 10777277Abstract: Memories having a controller configured to perform methods during programming operations including applying a first voltage level to first and second data lines while applying a second, lower, voltage level to first and second select gates connected between the data lines and respective strings of memory cells; decreasing a voltage level of the first data line to a third voltage level; increasing a voltage level of the first select gate to a fourth voltage level; applying a fifth voltage level, higher than the first voltage level, to first and second access lines coupled to memory cells of the strings of memory cells; and increasing a voltage level of the first access line to a sixth voltage level.Type: GrantFiled: October 17, 2019Date of Patent: September 15, 2020Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Purval S. Sule, Han Liu, Andrea D'Alessandro, Pranav Kalavade, Han Zhao, Shantanu Rajwade
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Publication number: 20200066350Abstract: Memories having a controller configured to perform methods during programming operations including applying a first voltage level to first and second data lines while applying a second, lower, voltage level to first and second select gates connected between the data lines and respective strings of memory cells; decreasing a voltage level of the first data line to a third voltage level; increasing a voltage level of the first select gate to a fourth voltage level; applying a fifth voltage level, higher than the first voltage level, to first and second access lines coupled to memory cells of the strings of memory cells; and increasing a voltage level of the first access line to a sixth voltage level.Type: ApplicationFiled: October 17, 2019Publication date: February 27, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Violante Moschiano, Purval S. Sule, Han Liu, Andrea D'Alessandro, Pranav Kalavade, Han Zhao, Shantanu Rajwade
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Patent number: 10482974Abstract: Methods include applying a first voltage level to first and second data lines while applying a second, lower, voltage level to first and second select gates connected between the data lines and respective strings of memory cells; decreasing a voltage level of the first data line to a third voltage level; increasing a voltage level of the first select gate to a fourth voltage level; applying a fifth voltage level, higher than the first voltage level, to first and second access lines coupled to memory cells of the strings of memory cells; and increasing a voltage level of the first access line to a sixth voltage level.Type: GrantFiled: August 21, 2018Date of Patent: November 19, 2019Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Purval S. Sule, Han Liu, Andrea D'Alessandro, Pranav Kalavade, Han Zhao, Shantanu Rajwade
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Publication number: 20190043567Abstract: An apparatus and/or system is described including a memory device or a controller for a memory device to perform an adjustment of a read operation time for data stored in the memory device. In embodiments, the apparatus may receive a request for data stored in the memory device and a read operation time adjustment module operable by the controller may acquire a first operation temperature of the memory device, obtained at a time of programming of the data stored in the memory device. The apparatus may acquire a second operation temperature of the memory device, obtained after the request for the data stored in the memory device is received. Based at least partially on the first operation temperature and the second operation temperature, the apparatus may adjust the read operation time to read the data. Other embodiments are disclosed and claimed.Type: ApplicationFiled: August 28, 2018Publication date: February 7, 2019Inventors: Ali Khakifirooz, Shantanu Rajwade, Rohit Shenoy, Aliasgar Madraswala, Pranav Kalavade