Patents by Inventor Shanyong Cao

Shanyong Cao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Clock and data recovery system, phase adjusting method, and phasedetector
    Patent number: 8624630
    Abstract: Disclosed is a phase discriminator, including: a first XOR gate connected to a trigger and a delay unit, a second XOR gate connected to the trigger and a latch, wherein the first XOR gate is a current mode logic XOR gate, the first XOR gate comprises a first offset current source circuit outputting a first adjustable offset circuit for controlling amplitude of the error signal output by the first XOR gate; and/or, the second XOR gate is a current mode logic XOR gate, the second XOR gate comprises a second offset current source circuit outputting a second adjustable offset circuit for controlling amplitude of reference signal output by the second XOR gate. Also disclosed are a clock and data recovery system and a phase adjustment method. The present invention can prevent introducing noise coupling to the voltage control oscillator (VCO) module.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: January 7, 2014
    Assignee: ZTE Corporation
    Inventors: Jiansheng Liao, Shanyong Cao
  • CLOCK AND DATA RECOVERY SYSTEM, PHASE ADJUSTING METHOD, AND PHASEDETECTOR
    Publication number: 20120293226
    Abstract: Disclosed is a phase discriminator, including: a first XOR gate connected to a trigger and a delay unit, a second XOR gate connected to the trigger and a latch, wherein the first XOR gate is a current mode logic XOR gate, the first XOR gate comprises a first offset current source circuit outputting a first adjustable offset circuit for controlling amplitude of the error signal output by the first XOR gate; and/or, the second XOR gate is a current mode logic XOR gate, the second XOR gate comprises a second offset current source circuit outputting a second adjustable offset circuit for controlling amplitude of reference signal output by the second XOR gate. Also disclosed are a clock and data recovery system and a phase adjustment method. The present invention can prevent introducing noise coupling to the voltage control oscillator (VCO) module.
    Type: Application
    Filed: April 18, 2011
    Publication date: November 22, 2012
    Inventors: Jiansheng Liao, Shanyong Cao