Patents by Inventor Shao-Chi Yu
Shao-Chi Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9614031Abstract: A high-voltage super junction device is disclosed. The device includes a semiconductor substrate region having a first conductivity type and having neighboring trenches disposed therein. The neighboring trenches each have trench sidewalls and a trench bottom surface. A region having a second conductivity type is disposed in or adjacent to a trench and meets the semiconductor substrate region at a p-n junction. A gate electrode is formed on the semiconductor substrate region and is electrically isolated from the semiconductor substrate region by a gate dielectric. A body region having the second conductivity type is disposed on opposite sides of the gate electrode near a surface of the semiconductor substrate. A source region having the first conductivity type is disposed within in the body region on opposite sides of the gate electrode near the surface of the semiconductor substrate.Type: GrantFiled: July 23, 2015Date of Patent: April 4, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-I Yang, Shou-Wei Lee, Shao-Chi Yu, Hong-Seng Shue, Kun-Ming Huang, Po-Tao Chu
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Patent number: 9567204Abstract: A method for manufacturing a microelectromechanical systems (MEMS) device is provided. According to the method, a semiconductor structure is provided. The semiconductor structure includes an integrated circuit (IC) substrate, a dielectric layer arranged over the IC substrate, and a MEMS substrate arranged over the IC substrate and the dielectric layer to define a cavity between the MEMS substrate and the IC substrate. The MEMS substrate includes a MEMS hole in fluid communication with the cavity and extending through the MEMS substrate. A sealing layer is formed over or lining the MEMS hole to hermetically seal the cavity with a reference pressure while the semiconductor structure is arranged within a vacuum having the reference pressure. The semiconductor structure resulting from application of the method is also provided.Type: GrantFiled: August 29, 2014Date of Patent: February 14, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Ming Hung, Shao-Chi Yu, Hsiang-Fu Chen, Wen-Chuan Tai, Hsin-Ting Huang
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Publication number: 20160264402Abstract: The present disclosure relates to a wafer level chip scale package (WLCSP) with a stress absorbing cap substrate. The cap substrate is bonded to a die through a bond ring and a bond pad arranged on an upper surface of the cap substrate. A through substrate via (TSV) extends from the bond pad, through the cap substrate, to a lower surface of the cap substrate. Further, recesses in the upper surface extend around the bond pad and along sidewalls of the bond ring. The recesses absorb induced stress, thereby mitigating any device offset in the die.Type: ApplicationFiled: March 12, 2015Publication date: September 15, 2016Inventors: Shao-Chi Yu, Chia-Ming Hung, Hsin-Ting Huang, Hsiang-Fu Chen, Allen Timothy Chang, Wen-Chuan Tai
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Publication number: 20160266061Abstract: The present disclosure is directed to a monolithic MEMS (micro-electromechanical system) platform having a temperature sensor, a pressure sensor and a gas sensor, and an associated method of formation. In some embodiments, the MEMS platform includes a semiconductor substrate having one or more transistor devices and a temperature sensor. A dielectric layer is disposed over the semiconductor substrate. A cavity is disposed within an upper surface of the dielectric layer. A MEMS substrate is arranged onto the upper surface of the dielectric layer and has a first section and a second section. A pressure sensor has a first pressure sensor electrode that is vertically separated by the cavity from a second pressure sensor electrode within the first section of a MEMS substrate. A gas sensor has a polymer disposed between a first gas sensor electrode within the second section of a MEMS substrate and a second gas sensor electrode.Type: ApplicationFiled: March 12, 2015Publication date: September 15, 2016Inventors: Shao-Chi Yu, Chia-Ming Hung, Hsin-Ting Huang, Hsiang-Fu Chen, Wen-Chuan Tai
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Publication number: 20160214855Abstract: A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate.Type: ApplicationFiled: January 28, 2015Publication date: July 28, 2016Inventors: Ping Chun YEH, Lien-Yao TSAI, Shao-Chi YU
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Publication number: 20160172250Abstract: A device includes a semiconductor substrate, a contact plug over the semiconductor substrate, and an Inter-Layer Dielectric (ILD) layer over the semiconductor substrate, with the contact plug being disposed in the ILD. An air gap is sealed by a portion of the ILD and the semiconductor substrate. The air gap forms a full air gap ring encircling a portion of the semiconductor substrate.Type: ApplicationFiled: February 22, 2016Publication date: June 16, 2016Inventors: Hong-Seng Shue, Tai-I Yang, Wei-Ding Wu, Ming-Tai Chung, Shao-Chi Yu
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Publication number: 20160130137Abstract: Some embodiments relate to multiple MEMS devices that are integrated together on a single substrate. A device substrate comprising first and second micro-electro mechanical system (MEMS) devices is bonded to a capping structure. The capping structure comprises a first cavity arranged over the first MEMS device and a second cavity arranged over the second MEMS device. The first cavity is filled with a first gas at a first gas pressure. The second cavity is filled with a second gas at a second gas pressure, which is different from the first gas pressure. A recess is arranged within a lower surface of the capping structure. The recess abuts the second cavity. A vent is arranged within the capping structure. The vent extends from a top of the recess to the upper surface of the capping structure. A lid is arranged within the vent and configured to seal the second cavity.Type: ApplicationFiled: December 2, 2014Publication date: May 12, 2016Inventors: Hsin-Ting Huang, Hsiang-Fu Chen, Wen-Chuan Tai, Shao-Chi Yu, Chia-Ming Hung, Allen Timothy Chang, Bruce C.S. Chou, Chin-Min Lin
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Publication number: 20160060103Abstract: A method for manufacturing a microelectromechanical systems (MEMS) device is provided. According to the method, a semiconductor structure is provided. The semiconductor structure includes an integrated circuit (IC) substrate, a dielectric layer arranged over the IC substrate, and a MEMS substrate arranged over the IC substrate and the dielectric layer to define a cavity between the MEMS substrate and the IC substrate. The MEMS substrate includes a MEMS hole in fluid communication with the cavity and extending through the MEMS substrate. A sealing layer is formed over or lining the MEMS hole to hermetically seal the cavity with a reference pressure while the semiconductor structure is arranged within a vacuum having the reference pressure. The semiconductor structure resulting from application of the method is also provided.Type: ApplicationFiled: August 29, 2014Publication date: March 3, 2016Inventors: Chia-Ming Hung, Shao-Chi Yu, Hsiang-Fu Chen, Wen-Chuan Tai, Hsin-Ting Huang
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Patent number: 9269609Abstract: A device includes a semiconductor substrate, a contact plug over the semiconductor substrate, and an Inter-Layer Dielectric (ILD) layer over the semiconductor substrate, with the contact plug being disposed in the ILD. An air gap is sealed by a portion of the ILD and the semiconductor substrate. The air gap forms a full air gap ring encircling a portion of the semiconductor substrate.Type: GrantFiled: June 1, 2012Date of Patent: February 23, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Seng Shue, Tai-I Yang, Wei-Ding Wu, Ming-Tai Chung, Shao-Chi Yu
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Publication number: 20160016789Abstract: The present disclosure relates to a MEMS device with a hermetic sealing structure, and an associated method. In some embodiments, a first die and a second die are bonded at a bond interface region to form a chamber. A conformal thin film structure is disposed covering an outer sidewall of the bond interface region to provide hermetic sealing. In some embodiments, the conformal thin film structure is a continuous thin layer covering an outer surface of the second die and a top surface of the first die. In some other embodiments, the conformal thin film structure comprises several discrete thin film patches disposed longitudinal.Type: ApplicationFiled: July 16, 2014Publication date: January 21, 2016Inventors: Shao-Chi Yu, Hsiang-Fu Chen, Hsin-Ting Huang, Chia-Ming Hung, Wen-Chuan Tai
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Patent number: 9202792Abstract: A method of providing a redistribution layer (RDL) and a through-silicon via (TSV) for a semiconductor package is disclosed. The method comprises preparing a wafer for bonding to a semiconductor package. The wafer comprises a low resistance substrate containing a RDL and a TSV for making an input/output (I/O) connection point of the semiconductor package available at another location. The RDL comprises a conduction path through the low resistance substrate that is bounded on two sides by an isolation trench. The TSV is bounded by the isolation trench and the RDL. Preparing the wafer for bonding may comprise preparing the isolation trench that bounds the conduction path for the RDL through the low resistance substrate and bounds a vertical conduction path in a pillar for the TSV in the low resistance substrate, filling the isolation trench with isolation trench material, and preparing a wafer bonding surface.Type: GrantFiled: April 25, 2014Date of Patent: December 1, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Shao-Chi Yu, Chia-Ming Hung, Hsiang-Fu Chen, Wen-Chuan Tai, Hsin-Ting Huang
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Publication number: 20150325642Abstract: A high-voltage super junction device is disclosed. The device includes a semiconductor substrate region having a first conductivity type and having neighboring trenches disposed therein. The neighboring trenches each have trench sidewalls and a trench bottom surface. A region having a second conductivity type is disposed in or adjacent to a trench and meets the semiconductor substrate region at a p-n junction. A gate electrode is formed on the semiconductor substrate region and electrically is electrically isolated from the semiconductor substrate region by a gate dielectric. A body region having the second conductivity type is disposed on opposite sides of the gate electrode near a surface of the semiconductor substrate. A source region having the first conductivity type is disposed within in the body region on opposite sides of the gate electrode near the surface of the semiconductor substrate.Type: ApplicationFiled: July 23, 2015Publication date: November 12, 2015Inventors: Tai-I Yang, Shou-Wei Lee, Shao-Chi Yu, Hong-Seng Shue, Kun-Ming Huang, Po-Tao Chu
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Publication number: 20150311168Abstract: A method of providing a redistribution layer (RDL) and a through-silicon via (TSV) for a semiconductor package is disclosed. The method comprises preparing a wafer for bonding to a semiconductor package. The wafer comprises a low resistance substrate containing a RDL and a TSV for making an input/output (I/O) connection point of the semiconductor package available at another location. The RDL comprises a conduction path through the low resistance substrate that is bounded on two sides by an isolation trench. The TSV is bounded by the isolation trench and the RDL. Preparing the wafer for bonding may comprise preparing the isolation trench that bounds the conduction path for the RDL through the low resistance substrate and bounds a vertical conduction path in a pillar for the TSV in the low resistance substrate, filling the isolation trench with isolation trench material, and preparing a wafer bonding surface.Type: ApplicationFiled: April 25, 2014Publication date: October 29, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: SHAO-CHI YU, CHIA-MING HUNG, HSIANG-FU CHEN, WEN-CHUAN TAI, HSIN-TING HUANG
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Publication number: 20150239732Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a MEMS device in a MEMS area, where a first metal layer is connected to a first metal connect adjacent the MEMS area and a cap is over the MEMS area to vacuum seal the MEMS area. A first wafer portion is over and bonded to the first metal layer which connects the first metal connect to a first I/O port using metal routing. The first metal layer and the first wafer portion bond requires 10% less bonding area than a bond not including the first metal layer. The semiconductor arrangement including the first metal layer has increased conductivity and requires less processing than an arrangement that requires a dopant implant to connect a first metal connect to a first I/O port and has a better vacuum seal due to a reduction in outgassing.Type: ApplicationFiled: February 26, 2014Publication date: August 27, 2015Inventors: Hsin-Ting Huang, Hsiang-Fu Chen, Wen-Chuan Tai, Chia-Ming Hung, Shao-Chi Yu, Hung-Hua Lin, Yuan-Chih Hsieh
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Patent number: 9093520Abstract: A high-voltage super junction device is disclosed. The device includes a semiconductor substrate region having a first conductivity type and having neighboring trenches disposed therein. The neighboring trenches each have trench sidewalls and a trench bottom surface. A region having a second conductivity type is disposed in or adjacent to a trench and meets the semiconductor substrate region at a p-n junction. A gate electrode is formed on the semiconductor substrate region and is electrically isolated from the semiconductor substrate region by a gate dielectric. A body region having the second conductivity type is disposed on opposite sides of the gate electrode near a surface of the semiconductor substrate. A source region having the first conductivity type is disposed within in the body region on opposite sides of the gate electrode near the surface of the semiconductor substrate.Type: GrantFiled: August 28, 2013Date of Patent: July 28, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-I Yang, Shou-Wei Lee, Shao-Chi Yu, Hong-Seng Shue, Kun-Ming Huang, Po-Tao Chu
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Publication number: 20150061007Abstract: A high-voltage super junction device is disclosed. The device includes a semiconductor substrate region having a first conductivity type and having neighboring trenches disposed therein. The neighboring trenches each have trench sidewalls and a trench bottom surface. A region having a second conductivity type is disposed in or adjacent to a trench and meets the semiconductor substrate region at a p-n junction. A gate electrode is formed on the semiconductor substrate region and electrically is electrically isolated from the semiconductor substrate region by a gate dielectric. A body region having the second conductivity type is disposed on opposite sides of the gate electrode near a surface of the semiconductor substrate. A source region having the first conductivity type is disposed within in the body region on opposite sides of the gate electrode near the surface of the semiconductor substrate.Type: ApplicationFiled: August 28, 2013Publication date: March 5, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-I Yang, Shou-Wei Lee, Shao-Chi Yu, Hong-Seng Shue, Kun-Ming Huang, Po-Tao Chu
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Publication number: 20130320459Abstract: A device includes a semiconductor substrate, a contact plug over the semiconductor substrate, and an Inter-Layer Dielectric (ILD) layer over the semiconductor substrate, with the contact plug being disposed in the ILD. An air gap is sealed by a portion of the ILD and the semiconductor substrate. The air gap forms a full air gap ring encircling a portion of the semiconductor substrate.Type: ApplicationFiled: June 1, 2012Publication date: December 5, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hong-Seng Shue, Tai-I Yang, Wei-Ding Wu, Ming-Tai Chung, Shao-Chi Yu
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Patent number: 8558330Abstract: A micromechanical systems (MEMs) pressure sensor includes a semiconductor substrate having a deep well located within a first surface and a cavity located within a second, opposing surface. The semiconductor substrate has a first doping type. The deep well has a second doping type, with a gradient doping profile, thereby forming a PN junction within the substrate. The cavity forms a diaphragm, which is a substrate section that is thinner than the surrounding substrate sections, that comprises the deep well. One or more pizeoresistor elements are located within the deep well. The piezoresistors are sensitive to deformations, such as bending, in the diaphragm caused by changes in the pressure of the cavity.Type: GrantFiled: July 5, 2012Date of Patent: October 15, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shao-Chi Yu, Hong-Seng Shue
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Publication number: 20130105923Abstract: A micromechanical systems (MEMs) pressure sensor includes a semiconductor substrate having a deep well located within a first surface and a cavity located within a second, opposing surface. The semiconductor substrate has a first doping type. The deep well has a second doping type, with a gradient doping profile, thereby forming a PN junction within the substrate. The cavity forms a diaphragm, which is a substrate section that is thinner than the surrounding substrate sections, that comprises the deep well. One or more pizeoresistor elements are located within the deep well. The piezoresistors are sensitive to deformations, such as bending, in the diaphragm caused by changes in the pressure of the cavity.Type: ApplicationFiled: July 5, 2012Publication date: May 2, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shao-Chi Yu, Hong-Seng Shue