Patents by Inventor Shao Hsuan CHUANG

Shao Hsuan CHUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240168238
    Abstract: A recessed portion in a semiconductor substrate and a method of forming the same are provided. The method comprises: forming a mask on the semiconductor substrate; forming a protection layer on a top surface of the mask and on at least one sidewall of the mask, and on at least one surface of the semiconductor substrate exposed by the mask; performing a first etching process to remove the protection layer on the top surface of the mask and on a bottom surface of the semiconductor substrate exposed by the mask; and performing a second etching process to remove the remaining protection layer and to etch the semiconductor substrate to form the recessed portion. In this way, a recessed portion with relatively smooth and vertical sidewalls can be realized.
    Type: Application
    Filed: January 30, 2024
    Publication date: May 23, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shao Hsuan CHUANG, Huang-Hsien CHANG
  • Patent number: 11886015
    Abstract: A recessed portion in a semiconductor substrate and a method of forming the same are provided. The method comprises: forming a mask on the semiconductor substrate; forming a protection layer on a top surface of the mask and on at least one sidewall of the mask, and on at least one surface of the semiconductor substrate exposed by the mask; performing a first etching process to remove the protection layer on the top surface of the mask and on a bottom surface of the semiconductor substrate exposed by the mask; and performing a second etching process to remove the remaining protection layer and to etch the semiconductor substrate to form the recessed portion. In this way, a recessed portion with relatively smooth and vertical sidewalls can be realized.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: January 30, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shao Hsuan Chuang, Huang-Hsien Chang
  • Patent number: 11848143
    Abstract: An electronic device and a method for manufacturing an electronic device are provided. The electronic device includes an inductor. The inductor includes a plurality of line portions and a plurality of plate portions connected to the plurality of line portions. The line portions and the plate portions form a coil concentric to a horizontal axis.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: December 19, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yunghsun Chen, Huang-Hsien Chang, Shao Hsuan Chuang
  • Publication number: 20230027674
    Abstract: A semiconductor device and method for manufacturing the same are provided. The method includes providing a first substrate. The method also includes forming a first metal layer on the first substrate. The first metal layer includes a first metal material. The method further includes treating a first surface of the first metal layer with a solution including an ion of a second metal material. In addition, the method includes forming a plurality of metal particles including the second metal material on a portion of the first surface of the first metal layer.
    Type: Application
    Filed: September 30, 2022
    Publication date: January 26, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jhao-Cheng CHEN, Huang-Hsien CHANG, Wen-Long LU, Shao Hsuan CHUANG, Ching-Ju CHEN, Tse-Chuan CHOU
  • Patent number: 11495557
    Abstract: A semiconductor device and method for manufacturing the same are provided. The method includes providing a first substrate. The method also includes forming a first metal layer on the first substrate. The first metal layer includes a first metal material. The method further includes treating a first surface of the first metal layer with a solution including an ion of a second metal material. In addition, the method includes forming a plurality of metal particles including the second metal material on a portion of the first surface of the first metal layer.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: November 8, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jhao-Cheng Chen, Huang-Hsien Chang, Wen-Long Lu, Shao Hsuan Chuang, Ching-Ju Chen, Tse-Chuan Chou
  • Patent number: 11410957
    Abstract: At least some embodiments of the present disclosure relate to a method for manufacturing a bonding structure. The method includes: providing a substrate with a seed layer; forming a conductive pattern on the seed layer; forming a dielectric layer on the substrate and the conductive pattern; and removing a portion of the dielectric layer to expose an upper surface of the conductive pattern without consuming the seed layer.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: August 9, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shao Hsuan Chuang, Huang-Hsien Chang
  • Patent number: 11411073
    Abstract: A semiconductor package device includes a first conductive wall, a second conductive wall, a first insulation wall, a dielectric layer, a first electrode, and a second electrode. The first insulation wall is disposed between the first and second conductive walls. The dielectric layer has a first portion covering a bottom surface of the first conductive wall, a bottom surface of the second conductive wall and a bottom surface of the first insulation wall. The first electrode is electrically connected to the first conductive wall. The second electrode is electrically connected to the second conductive wall.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: August 9, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shao Hsuan Chuang, Huang-Hsien Chang, Min Lung Huang
  • Publication number: 20220236489
    Abstract: A recessed portion in a semiconductor substrate and a method of forming the same are provided. The method comprises: forming a mask on the semiconductor substrate; forming a protection layer on a top surface of the mask and on at least one sidewall of the mask, and on at least one surface of the semiconductor substrate exposed by the mask; performing a first etching process to remove the protection layer on the top surface of the mask and on a bottom surface of the semiconductor substrate exposed by the mask; and performing a second etching process to remove the remaining protection layer and to etch the semiconductor substrate to form the recessed portion. In this way, a recessed portion with relatively smooth and vertical sidewalls can be realized.
    Type: Application
    Filed: March 1, 2022
    Publication date: July 28, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shao Hsuan CHUANG, Huang-Hsien CHANG
  • Patent number: 11398442
    Abstract: A bonding structure, a package structure, and a method for manufacturing a package structure are provided. The package structure includes a first substrate, a first passivation layer, a first conductive layer, and a first conductive bonding structure. The first passivation layer is disposed on the first substrate and has an upper surface. The first passivation layer and the first substrate define a first cavity. The first conductive layer is disposed in the first cavity and has an upper surface. A portion of the upper surface of the first conductive layer is below the upper surface of the first passivation layer. The first conductive bonding structure is disposed on the first conductive layer.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: July 26, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wan Yu Chang, Shao Hsuan Chuang
  • Publication number: 20220139854
    Abstract: A bonding structure, a package structure, and a method for manufacturing a package structure are provided. The package structure includes a first substrate, a first passivation layer, a first conductive layer, and a first conductive bonding structure. The first passivation layer is disposed on the first substrate and has an upper surface. The first passivation layer and the first substrate define a first cavity. The first conductive layer is disposed in the first cavity and has an upper surface. A portion of the upper surface of the first conductive layer is below the upper surface of the first passivation layer. The first conductive bonding structure is disposed on the first conductive layer.
    Type: Application
    Filed: October 29, 2020
    Publication date: May 5, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wan Yu CHANG, Shao Hsuan CHUANG
  • Publication number: 20220108826
    Abstract: An electronic device and a method for manufacturing an electronic device are provided. The electronic device includes an inductor. The inductor includes a plurality of line portions and a plurality of plate portions connected to the plurality of line portions. The line portions and the plate portions form a coil concentric to a horizontal axis.
    Type: Application
    Filed: October 7, 2020
    Publication date: April 7, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yunghsun CHEN, Huang-Hsien CHANG, Shao Hsuan CHUANG
  • Patent number: 11262506
    Abstract: A recessed portion in a semiconductor substrate and a method of forming the same are provided. The method comprises: forming a mask on the semiconductor substrate; forming a protection layer on a top surface of the mask and on at least one sidewall of the mask, and on at least one surface of the semiconductor substrate exposed by the mask; performing a first etching process to remove the protection layer on the top surface of the mask and on a bottom surface of the semiconductor substrate exposed by the mask; and performing a second etching process to remove the remaining protection layer and to etch the semiconductor substrate to form the recessed portion. In this way, a recessed portion with relatively smooth and vertical sidewalls can be realized.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: March 1, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shao Hsuan Chuang, Huang-Hsien Chang
  • Publication number: 20220043215
    Abstract: A recessed portion in a semiconductor substrate and a method of forming the same are provided. The method comprises: forming a mask on the semiconductor substrate; forming a protection layer on a top surface of the mask and on at least one sidewall of the mask, and on at least one surface of the semiconductor substrate exposed by the mask; performing a first etching process to remove the protection layer on the top surface of the mask and on a bottom surface of the semiconductor substrate exposed by the mask; and performing a second etching process to remove the remaining protection layer and to etch the semiconductor substrate to form the recessed portion. In this way, a recessed portion with relatively smooth and vertical sidewalls can be realized.
    Type: Application
    Filed: August 7, 2020
    Publication date: February 10, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shao Hsuan CHUANG, Huang-Hsien CHANG
  • Publication number: 20220028817
    Abstract: At least some embodiments of the present disclosure relate to a method for manufacturing a bonding structure. The method includes: providing a substrate with a seed layer; forming a conductive pattern on the seed layer; forming a dielectric layer on the substrate and the conductive pattern; and removing a portion of the dielectric layer to expose an upper surface of the conductive pattern without consuming the seed layer.
    Type: Application
    Filed: July 23, 2020
    Publication date: January 27, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shao Hsuan CHUANG, Huang-Hsien CHANG
  • Publication number: 20210296267
    Abstract: A semiconductor device and method for manufacturing the same are provided. The method includes providing a first substrate. The method also includes forming a first metal layer on the first substrate. The first metal layer includes a first metal material. The method further includes treating a first surface of the first metal layer with a solution including an ion of a second metal material. In addition, the method includes forming a plurality of metal particles including the second metal material on a portion of the first surface of the first metal layer.
    Type: Application
    Filed: March 20, 2020
    Publication date: September 23, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jhao-Cheng CHEN, Huang-Hsien CHANG, Wen-Long LU, Shao Hsuan CHUANG, Ching-Ju CHEN, Tse-Chuan CHOU
  • Patent number: 11107881
    Abstract: The subject application relates to a semiconductor package device, which includes a first conductive layer; a semiconductor wall disposed on the first conductive layer; a first conductive wall disposed on the first conductive layer; and an insulation layer disposed on the first conductive layer and between the semiconductor wall and the first conductive wall.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: August 31, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shao Hsuan Chuang, Huang-Hsien Chang, Min Lung Huang, Yu Cheng Chen, Syu-Tang Liu
  • Publication number: 20210265459
    Abstract: A semiconductor package device includes a first conductive wall, a second conductive wall, a first insulation wall, a dielectric layer, a first electrode, and a second electrode. The first insulation wall is disposed between the first and second conductive walls. The dielectric layer has a first portion covering a bottom surface of the first conductive wall, a bottom surface of the second conductive wall and a bottom surface of the first insulation wall. The first electrode is electrically connected to the first conductive wall. The second electrode is electrically connected to the second conductive wall.
    Type: Application
    Filed: February 26, 2020
    Publication date: August 26, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shao Hsuan CHUANG, Huang-Hsien CHANG, Min Lung HUANG
  • Publication number: 20200343336
    Abstract: The subject application relates to a semiconductor package device, which includes a first conductive layer; a semiconductor wall disposed on the first conductive layer; a first conductive wall disposed on the first conductive layer; and an insulation layer disposed on the first conductive layer and between the semiconductor wall and the first conductive wall.
    Type: Application
    Filed: April 25, 2019
    Publication date: October 29, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shao Hsuan CHUANG, Huang-Hsien CHANG, Min Lung HUANG, Yu Cheng CHEN, Syu-Tang LIU