Abstract: An interface circuitry includes an interface, a transmitter module and a receiver module. The transmitter module includes an input stage, a driving circuit and a regulator circuit. The input stage is powered by a regulated voltage and configured to receive an input signal and generate a first output signal and a second output signal. The driving circuit is configured to drive the interface according to the first output signal and the second output signal and to provide a first data signal, a second data signal and a driving signal. The regulator circuit is coupled between the input stage and the driving circuit, and configured to provide the supply voltage according to the driving current.

Abstract: Introduced here are techniques for implementing a clock and data recovery circuit with improved tendencies, such a pull up and/or pull down tendencies. In various embodiments, the CDR circuit includes a phase detector that receives an input signal and a output reference clock signal. The phase detector then outputs two signals to charge pump. The output from the charge pump drives an oscillator control voltage up or down depending the current from the charge pump. A lock detector detects whether a lock has occurred by comparing the oscillator control voltage to a predetermined threshold voltage. A lock can occur when the circuit has settled into a frequency substantially near the frequency of the input signal and the oscillator control voltage is substantially near the threshold voltage. A controller circuit can control a sweeping of an available frequency range by the circuit until a lock occurs.

Abstract: A HDMI apparatus is provided. The HDMI apparatus includes a first audio/video transceiver (A/V transceiver) configured to transmit an optical A/V signal to a second A/V transceiver; and a first sideband transceiver configured to drive a first laser diode to transmit a first optical sideband signal including a first control information or a first power information; wherein the first control information or the first power information is converted by a first Serializer/Deserializer (SERDES).

Abstract: A HDMI apparatus is provided. The HDMI apparatus includes a first audio/video transceiver (A/V transceiver) configured to transmit an optical A/V signal to a second A/V transceiver; and a first sideband transceiver configured to drive a first laser diode to transmit a first optical sideband signal including a first control information or a first power information; wherein the first control information or the first power information is converted by a first Serializer/Deserializer (SERDES).

Abstract: Introduced here are techniques for implementing a clock and data recovery circuit with improved tendencies, such a pull up and/or pull down tendencies. In various embodiments, the CDR circuit includes a phase detector that receives an input signal and a output reference clock signal. The phase detector then outputs two signals to charge pump. The output from the charge pump drives an oscillator control voltage up or down depending the current from the charge pump. A lock detector detects whether a lock has occurred by comparing the oscillator control voltage to a predetermined threshold voltage. A lock can occur when the circuit has settled into a frequency substantially near the frequency of the input signal and the oscillator control voltage is substantially near the threshold voltage. A controller circuit can control a sweeping of an available frequency range by the circuit until a lock occurs.

Abstract: A HDMI apparatus is provided. The HDMI apparatus includes a first audio/video transceiver (A/V transceiver) configured to transmit an optical A/V signal to a second A/V transceiver; and a first sideband transceiver configured to drive a first laser diode to transmit a first optical sideband signal including a first control information or a first power information; wherein the first control information or the first power information is converted by a first Serializer/Deserializer (SERDES).

Abstract: In a power switching apparatus, a first switch includes a first end coupled to a first input terminal, a second end coupled to an output terminal, and a control end coupled to a second input terminal and coupled to a ground via a first resistor. A second resistor is coupled between the output terminal and the ground. A second switch includes a first end coupled to the second input terminal, a second end coupled to the output terminal and a control end coupled to the ground via a third resistor. A third switch includes a first end coupled to the control end of the second switch and the first end of the third resistor, a second end coupled to the first input terminal and a control end coupled to the second input terminal and coupled to the ground via the first resistor.

Abstract: An interface circuitry includes an interface, a transmitter module and a receiver module. The transmitter module includes an input stage, a driving circuit and a regulator circuit. The input stage is powered by a regulated voltage and configured to receive an input signal and generate a first output signal and a second output signal. The driving circuit is configured to drive the interface according to the first output signal and the second output signal and to provide a first data signal, a second data signal and a driving signal. The regulator circuit is coupled between the input stage and the driving circuit, and configured to provide the supply voltage according to the driving current.

Abstract: In a power switching apparatus, a first switch includes a first end coupled to a first input terminal, a second end coupled to an output terminal, and a control end coupled to a second input terminal and coupled to a ground via a first resistor. A second resistor is coupled between the output terminal and the ground. A second switch includes a first end coupled to the second input terminal, a second end coupled to the output terminal and a control end coupled to the ground via a third resistor. A third switch includes a first end coupled to the control end of the second switch and the first end of the third resistor, a second end coupled to the first input terminal and a control end coupled to the second input terminal and coupled to the ground via the first resistor.

Abstract: A HDMI apparatus is provided. The HDMI apparatus includes a first audio/video transceiver (A/V transceiver) configured to transmit an optical A/V signal to a second A/V transceiver; and a first sideband transceiver configured to drive a first laser diode to transmit a first optical sideband signal including a first control information or a first power information; wherein the first control information or the first power information is converted by a first Serializer/Deserializer (SERDES).

Abstract: A clock and data recovery circuit includes a sampler, a skew compensation block, a pulse generator, and an injection locked oscillator. The injection locked oscillator generates a recovered clock signal, the pulse generator generates a pulse signal according to input data for controlling the injection locked oscillator, the skew compensation block compensates the input data and generate compensated data, and the sampler samples the compensated data according to the recovered clock signal.

Abstract: A clock and data recovery circuit includes a sampler, a skew compensation block, a pulse generator, and an injection locked oscillator. The injection locked oscillator generates a recovered clock signal, the pulse generator generates a pulse signal according to input data for controlling the injection locked oscillator, the skew compensation block compensates the input data and generate compensated data, and the sampler samples the compensated data according to the recovered clock signal.

Abstract: A clock and data recovery circuit includes a sampler, a skew compensation block, a pulse generator, and an injection locked oscillator. The injection locked oscillator generates a recovered clock signal, the pulse generator generates a pulse signal according to input data for controlling the injection locked oscillator, the skew compensation block compensates the input data and generate compensated data, and the sampler samples the compensated data according to the recovered clock signal.

Abstract: A clock and data recovery circuit includes a sampler, a skew compensation block, a pulse generator, and an injection locked oscillator. The injection locked oscillator generates a recovered clock signal, the pulse generator generates a pulse signal according to input data for controlling the injection locked oscillator, the skew compensation block compensates the input data and generate compensated data, and the sampler samples the compensated data according to the recovered clock signal.