Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for decoding information.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit. The data detector circuit includes an anti-causal noise predictive filter circuit and a data detection circuit. In some cases, the anti-causal noise predictive filter circuit is operable to apply noise predictive filtering to a detector input to yield a filtered output, and the data detection circuit is operable to apply a data detection algorithm to the filtered output derived from the anti-causal noise predictive filter circuit.

Abstract: The present invention is related to systems and methods for data storage compression.

Abstract: Various embodiments of the present invention provide systems and methods for format efficient data storage. As an example, a data storage device is described that includes: a storage medium, a read/write head assembly, and a read channel circuit. The read/write head assembly is disposed in relation to the storage medium and operable to sense information corresponding to an encoded codeword. The read channel circuit is operable to receive the encoded codeword. The read channel circuit includes a missing symbols insertion circuit, a codeword de-scramble circuit, an address insertion circuit, and a data decoder circuit. The missing symbols insertion circuit, the codeword de-scramble circuit, and the address insertion circuit together are operable to pad a derivative of the encoded codeword with a plurality of symbols, to de-scramble the derivative of the encoded codeword, and to insert address information corresponding to the derivative of the encoded codeword to yield a modified encoded codeword.

Abstract: The present inventions are related to systems and methods for information data processing included selective decoder message determination. In one example, a data processing system is disclosed that includes a data decoder circuit operable to apply a conditional data decoding algorithm to a data set to yield a decoded output. The conditional decoding algorithm is operable to calculate node messages using an approach selected from a group consisting of: a first message determination mechanism, and a second message determination mechanism; where one of the first message determination mechanism and the second message determination mechanism is selected based upon a condition that includes a global iteration count applied to the data set.

Abstract: The present inventions are related to systems and methods for decoding data in an LDPC layer decoder for LDPC codes with overlapped circulants.

Abstract: An apparatus for low density parity check decoding includes a variable node processor operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages, a check node processor operable to generate the check node to variable node messages and to calculate checksums based on the variable node to check node messages, and a scheduler operable to determine a layer processing order for the variable node processor and the check node processor based at least in part on the number of unsatisfied parity checks for each of the H matrix layers.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding.

Abstract: A system and method for power management in a hard disk drive (HDD) assembly incorporating two or more read sensors includes directing a read/write head to follow a track; depowering one or more read sensors and readpath circuits associated with the read sensors; reading an analog readback signal through the first read sensor; processing the signal through an analog front-end to generate an input signal; sampling the input signal through an analog to digital converter at a first frequency to generate a first sampling signal; sampling the input signal through a second analog to digital converter at a second frequency to generate a second sampling signal; and generating a digital output signal from either or both sampling signals at a third sampling frequency through a digital signal processor. The method may additionally comprise adjusting a sampling frequency when power level reaches a threshold.

Abstract: A method of generating a hardware encoder includes generating a first directed graph characterizing a constraint set for a constrained system, identifying a scaling factor for an approximate eigenvector for the first directed graph, applying the scaling factor to the approximate eigenvector for the first directed graph to yield a scaled approximate eigenvector, partitioning arcs between each pair of states in the first directed graph, performing a state splitting operation on the first directed graph according to the partitioning of the arcs to yield a second directed graph, and generating the hardware encoder based on the second directed graph.

Abstract: Various systems and methods for media defect detection.

Abstract: A data processing system includes a decoder circuit, syndrome calculation circuit and hash calculation circuit. The decoder circuit is operable to apply a decoding algorithm to a decoder input based on a first portion of a composite matrix to yield a codeword. The syndrome calculation circuit is operable to calculate a syndrome based on the codeword and on the first portion of the composite matrix. The hash calculation circuit is operable to calculate a hash based on a second portion of the composite matrix. The decoder circuit is also operable to correct the codeword on the hash when the syndrome indicates that the codeword based on the first portion of the composite matrix is correct but a second test indicates that the codeword is miscorrected.

Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for combining recovered portions of a data set.

Abstract: A LDPC decoder includes a processor for targeted symbol flipping of suspicious bits in a LDPC codeword with unsatisfied checks. All combinations of check indices and variable indices are compiled and correlated into a pool of targeted symbol flipping candidates and returned along with symbol indices to a process that uses such symbol indices to identify symbols to flip in order to break a trapping set.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for variable rate encoding and/or decoding in a data processing system. In some cases, embodiments include a variable length data decoder circuit that is operable to apply a decode algorithm to the encoded input based upon a first selected H-Matrix to yield a first decoded output and apply the decode algorithm to the encoded input based upon a second selected H-Matrix to yield a second decoded output.

Abstract: A method for finding a valid codeword based on a near codeword trapping in a low-density parity-check decoding process includes identifying trapping set configurations and applying corrections to produce trapping sets with a limited number of invalid checks. Trapping set configurations are corrected in order to produce a trapping set in a table of trapping sets, the table associating each corrected trapping set with a valid codeword.

Abstract: A layered LDPC decoder architecture includes a single MUX and a single shifter element for processing an optimized LDPC parity check matrix. The optimized LDPC parity check matrix may be a K×L sub-matrix having zero elements, non-zero elements defined by a circulant matrix or zero matrices, and identity matrixes.

Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for encoding and decoding information.

Abstract: The present invention is related to systems and methods for branch metric calculation based on multiple data streams in a data processing circuit.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system. In one particular case, a system is disclosed that includes a first data processing circuit operable to apply a data detection algorithm to a data input synchronous to a first clock, and a second data processing circuit operable to apply a subsequent data processing algorithm to an output derived from the first data processing circuit synchronous to a second clock, and an idle time enforcement circuit operable to modify an average frequency of at least one of the first clock and the second clock.