Abstract: An apparatus and method is presented for capacitance analysis in chip environments for arbitrary geometries. It uses a process which combines 2-dimensional ascertainments where the length is chosen to fit the solution. Also, the required accuracy may be limited to be within an error range. The technique is also applicable for the analysis of three dimensional capacitances, and importantly also for a mixture of two and three dimensional capacitance ascertainments. In an embodiment the process divides the space into a set of subspaces. The capacitance value for the subspaces are determined using the parallel plate capacitance formula.

Abstract: A data cache unit associated with a processor, the data cache unit including a multi-ported non-blocking cache receiving a data access request from a lower level device in the processor. A memory scheduling window includes at least one row of entries, wherein each entry includes an address field holding an address of the access request. A conflict map field within at least some of the entries is coupled to a conflict checking unit. The conflict checking unit responds to the address fields by setting bits in the conflict map fields to indicate intra-row conflicts between entries. A picker coupled to the memory scheduling window responds to the conflict map fields so as to identify groups of non-conflicting entries to launch in parallel at the multi-ported non-blocking cache.

Abstract: A method and system for providing parasitic capacitance estimation on interconnect data for an integrated circuit is disclosed. An integrated circuit typically includes a substrate layer and several metal layers. In accordance with the method and system of the present invention, a center wire within one of the several metal layers is first identified. Then, a first capacitance value between a first wire and the center wire as well as a second capacitance value between a second wire and the center wire are determined. The first wire, the second wire, and the center wire are in the same metal layer. Next, a third capacitance value between a third wire and the center wire is determined. This third wire is in a metal layer located directly beneath the center wire. Finally, a fourth capacitance value between a fourth wire and the center wire is determined. The fourth wire is in a metal layer located directly above the center wire.

Abstract: A method and system for characterizing interconnect data within an integrated circuit in order to facilitate parasitic capacitance estimation is disclosed. An integrated circuit typically includes a substrate layer and several metal layers. In accordance with the method and system of the present invention, an overlapping area of interconnect wires is first identified within the integrated circuit. This overlapping area, which is a polygon, may be formed between the substrate layer and at least one interconnect wire in one of the several metal layers. The overlapping area may also be formed between two interconnect wires, each in a different one of the several metal layers. A netname for the overlapping area is then recorded. Finally, a netname of an interconnect wire in a metal layer that is at the same level of an interconnect wire within the overlapping area and an associated distance from each side of the overlapping area is recorded, for every interconnect wire within the overlapping area.

Abstract: A computer processor which speculatively issues prefetch addresses for indirect as well as linear memory traversals after entering an armed state. A particular embodiment of the invention includes a central processing unit connected to an external memory through an interface. A cache memory, preferably integrated onto a processor chip with the central processing unit, is connected to both the central processing unit and the interface. A prefetch device is also preferably integrated onto the chip and selectively issues prefetch addresses after entering an armed state induced by recognized patterns in memory operand addresses of load instructions executed by the central processing unit. The prefetch device includes a recurrence recognition unit and a prefetch unit. When either the linear or indirect armed states are entered, the recurrence recognition unit will direct the prefetch unit to issue prefetch addresses according to a calculated linear or indirect stride.

Abstract: A synchronized clocking circuit receives a clock signal and, in accordance with the received clock signal, provides a divided-down clock signal having a known phase relationship with respect to the received clock signal upon reset. In order to provide the known phase relationship, and therefore to synchronize the received clock signal and the divided-down clock signal, a cycle of the divided down clock signal is selectably skipped. A reset signal is conditioned and applied to an active going edge detector. The cycle of the divided down clock is selectably skipped according to the active going edge detector.

Abstract: A method of searching a database having a plurality of objects is provided. Each object includes attributes and, for each attribute, a number of values. A query specifies two attributes and a maximum distance. A respective set of ranges is established for each object that has a value for the first attribute. Each set includes a range for each value of the first attribute. Each range is defined by minimum and maximum location values. A test range is established for one of the ranges. The test range has values equal to the minimum and maximum values of one of the ranges. The test range is adjusted, if necessary, so that it includes one of the values of the second attribute of the corresponding object. The test range is added to a group of ranges corresponding to the object if the minimum and maximum test values do not differ from one another by more than the maximum distance.