Patents by Inventor Sharon Duvdevani
Sharon Duvdevani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11651509Abstract: A method for process control of a semiconductor structure fabricated by a series of fabrication steps, the method comprising obtaining an image of the semiconductor structure indicative of at least two individual fabrication steps; wherein the image is generated by scanning the semiconductor structure with a charged particle beam and collecting signals emanating from the semiconductor structure; and processing, by a hardware processor, the image to determining a parameter of the semiconductor structure, wherein processing includes measuring step/s from among the fabrication steps as an individual feature.Type: GrantFiled: October 31, 2019Date of Patent: May 16, 2023Assignee: Applied Materials Israel Ltd.Inventors: Roman Kris, Roi Meir, Sahar Levin, Ishai Schwarzband, Grigory Klebanov, Shimon Levi, Efrat Noifeld, Hiroshi Miroku, Taku Yoshizawa, Kasturi Saha, Sharon Duvdevani-Bar, Vadim Vereschagin
-
Patent number: 11476081Abstract: A method, non-transitory computer readable medium and an evaluation system for evaluating an intermediate product related to a three dimensional NAND memory unit. The evaluation system may include an imager and a processing circuit. The imager may be configured to obtain, via an open gap, an electron image of a portion of a structural element that belongs to an intermediate product. The structural element may include a sequence of layers that include a top layer that is followed by alternating nonconductive layers and recessed conductive layers. The imager may include electron optics configured to scan the portion of the structural element with an electron beam that is oblique to a longitudinal axis of the open gap. The processing circuit is configured to evaluate the intermediate product based on the electron image. The open gap (a) exhibits a high aspect ratio, (b) has a width of nanometric scale, and (c) is formed between structural elements of the intermediate product.Type: GrantFiled: June 30, 2020Date of Patent: October 18, 2022Assignee: APPLIED MATERIALS ISRAEL LTD.Inventors: Roman Kris, Vadim Vereschagin, Assaf Shamir, Elad Sommer, Sharon Duvdevani-Bar, Meng Li Cecilia Lim
-
Patent number: 11443420Abstract: There is provided a system and method of generating a metrology recipe usable for examining a semiconductor specimen, comprising: obtaining a first image set comprising a plurality of first images captured by an examination tool, obtaining a second image set comprising a plurality of second images, wherein each second image is simulated based on at least one first image, wherein each second image is associated with ground truth data; performing a first test on the first image set and a second test on the second image set in accordance with a metrology recipe configured with a first parameter set, and determining, in response to a predetermined criterion not being met, to select a second parameter set, configure the metrology recipe with the second parameter set, and repeat the first test and the second test in accordance with the metrology recipe configured with the second parameter set.Type: GrantFiled: December 28, 2020Date of Patent: September 13, 2022Assignee: Applied Materials Israel Ltd.Inventors: Roman Kris, Grigory Klebanov, Einat Frishman, Tal Orenstein, Meir Vengrover, Noa Marom, Ilan Ben-Harush, Rafael Bistritzer, Sharon Duvdevani-Bar
-
Publication number: 20220207681Abstract: There is provided a system and method of generating a metrology recipe usable for examining a semiconductor specimen, comprising: obtaining a first image set comprising a plurality of first images captured by an examination tool, obtaining a second image set comprising a plurality of second images, wherein each second image is simulated based on at least one first image, wherein each second image is associated with ground truth data; performing a first test on the first image set and a second test on the second image set in accordance with a metrology recipe configured with a first parameter set, and determining, in response to a predetermined criterion not being met, to select a second parameter set, configure the metrology recipe with the second parameter set, and repeat the first test and the second test in accordance with the metrology recipe configured with the second parameter set.Type: ApplicationFiled: December 28, 2020Publication date: June 30, 2022Inventors: Roman KRIS, Grigory KLEBANOV, Einat FRISHMAN, Tal ORENSTEIN, Meir VENGROVER, Noa MAROM, Ilan BEN-HARUSH, Rafael BISTRITZER, Sharon DUVDEVANI-BAR
-
Publication number: 20210383529Abstract: A method for process control of a semiconductor structure fabricated by a series of fabrication steps, the method comprising obtaining an image of the semiconductor structure indicative of at least two individual fabrication steps; wherein the image is generated by scanning the semiconductor structure with a charged particle beam and collecting signals emanating from the semiconductor structure; and processing, by a hardware processor, the image to determining a parameter of the semiconductor structure, wherein processing includes measuring step/s from among the fabrication steps as an individual feature.Type: ApplicationFiled: October 31, 2019Publication date: December 9, 2021Inventors: Roman KRIS, Roi MEIR, Sahar LEVIN, Ishai SCHWARZBAND, Grigory KLEBANOV, Shimon LEVI, Efrat NOIFELD, Hiroshi MIROKU, Taku YOSHIZAWA, Kasturi SAHA, Sharon DUVDEVANI-BAR, Vadim VERESCHAGIN
-
Patent number: 11056404Abstract: An evaluation system that may include an imager; and a processing circuit. The imager may be configured to obtain an electron image of a hole that is formed by an etch process, the hole exposes at least one layer of a one or more sets of layers, each set of layers comprises layers that differ from each other by their electron yield and belong to an intermediate product. The processing circuit may be configured to evaluate, based on the electron image, whether the hole ended at a target layer of the intermediate product. The intermediate product is manufactured by one or more manufacturing stages of a manufacturing process of a three dimensional NAND memory unit. The hole may exhibit a high aspect ratio, and has a width of a nanometric scale.Type: GrantFiled: December 18, 2019Date of Patent: July 6, 2021Assignee: APPLIED MATERIALS ISRAEL LTD.Inventors: Roman Kris, Grigory Klebanov, Dhananjay Singh Rathore, Einat Frishman, Sharon Duvdevani-Bar, Assaf Shamir, Elad Sommer, Jannelle Anna Geva, Daniel Alan Rogers, Ido Friedler, Avi Aviad Ben Simhon
-
Publication number: 20210193536Abstract: An evaluation system that may include an imager; and a processing circuit. The imager may be configured to obtain an electron image of a hole that is formed by an etch process, the hole exposes at least one layer of a one or more sets of layers, each set of layers comprises layers that differ from each other by their electron yield and belong to an intermediate product. The processing circuit may be configured to evaluate, based on the electron image, whether the hole ended at a target layer of the intermediate product. The intermediate product is manufactured by one or more manufacturing stages of a manufacturing process of a three dimensional NAND memory unit. The hole may exhibit a high aspect ratio, and has a width of a nanometric scale.Type: ApplicationFiled: December 18, 2019Publication date: June 24, 2021Applicant: APPLIED MATERIALS ISRAEL LTD.Inventors: Roman Kris, Grigory Klebanov, Dhananjay Singh Rathore, Einat Frishman, Sharon Duvdevani-Bar, Assaf Shamir, Elad Sommer, Jannelle Anna Geva, Daniel Alan Rogers, Ido Friedler, Avi Aviad Ben Simhon
-
Publication number: 20210066026Abstract: A method, non-transitory computer readable medium and an evaluation system for evaluating an intermediate product related to a three dimensional NAND memory unit. The evaluation system may include an imager and a processing circuit. The imager may be configured to obtain, via an open gap, an electron image of a portion of a structural element that belongs to an intermediate product. The structural element may include a sequence of layers that include a top layer that is followed by alternating nonconductive layers and recessed conductive layers. The imager may include electron optics configured to scan the portion of the structural element with an electron beam that is oblique to a longitudinal axis of the open gap. The processing circuit is configured to evaluate the intermediate product based on the electron image. The open gap (a) exhibits a high aspect ratio, (b) has a width of nanometric scale, and (c) is formed between structural elements of the intermediate product.Type: ApplicationFiled: June 30, 2020Publication date: March 4, 2021Applicant: APPLIED MATERIALS ISRAEL LTD.Inventors: Roman Kris, Vadim Vereschagin, Assaf Shamir, Elad Sommer, Sharon Duvdevani-Bar, Meng Li Cecilia Lim
-
Patent number: 7388978Abstract: An electrical circuit inspection method including, for each of a plurality of types of local characteristics, each type occurring at least once within electrical circuitry to be inspected, identifying at least one portion of interest within the electrical circuitry whereat the local characteristic is expected to occur, and inspecting an image of each portion of interest, using an inspection task selected in response to the type of local characteristic expected to occur in the portion of interest.Type: GrantFiled: November 12, 2003Date of Patent: June 17, 2008Assignee: Orbotech Ltd.Inventors: Sharon Duvdevani, Tally Gilat-Bernshtein, Eyal Klingbell, Meir Mayo, Shmuel Rippa, Zeev Smilansky
-
Patent number: 7206443Abstract: A method for inspecting objects comprising: creating a reference image for a representative object, the reference image comprising an at least partially vectorized first representation of boundaries representing the representative object; acquiring an image of an object under inspection comprising a second representation of boundaries representing the object under inspection; and comparing a location of at least some boundaries in the second representation of boundaries to a location of corresponding boundaries in the at least partially vectorized first representation of boundaries, thereby to identify defects.Type: GrantFiled: August 7, 2000Date of Patent: April 17, 2007Assignee: Orbotech Ltd.Inventors: Sharon Duvdevani, Tally Gilat-Bernshtein, Eyal Klingbell, Meir Mayo, Shmuel Rippa, Zeev Smilansky
-
Patent number: 7181059Abstract: A method for inspecting electrical circuits, and a system for carrying out the method, generating a representation of boundaries of elements in an image of an electrical circuit which is under inspection, and analyzing at least some locations of at least some boundaries in the representation of boundaries of elements to identify defects in the electrical circuit.Type: GrantFiled: November 12, 2003Date of Patent: February 20, 2007Assignee: Orbotech Ltd.Inventors: Sharon Duvdevani, Tally Gilat-Bernshtein, Eyal Klingbell, Meir Mayo, Shmuel Rippa, Zeev Smilansky
-
Publication number: 20040126005Abstract: This invention discloses a system and method for inspecting objects, the method including creating a reference image for a representative object, the reference image comprising an at least partially vectorized first representation of boundaries within the image, acquiring an image of an object under inspection comprising a second representation of boundaries within the image, and comparing the second representation of boundaries to said at least partially vectorized first representation of boundaries, thereby to identify defects.Type: ApplicationFiled: November 12, 2003Publication date: July 1, 2004Applicant: ORBOTECH LTD.Inventors: Sharon Duvdevani, Tally Gilat-Bernshtein, Eyal Klingbell, Meir Mayo, Shmuel Rippa, Zeev Smilansky
-
Publication number: 20040120571Abstract: This invention discloses a system and method for inspecting objects, the method including creating a reference image for a representative object, the reference image comprising an at least partially vectorized first representation of boundaries within the image, acquiring an image of an object under inspection comprising a second representation of boundaries within the image, and comparing the second representation of boundaries to said at least partially vectorized first representation of boundaries, thereby to identify defects.Type: ApplicationFiled: November 12, 2003Publication date: June 24, 2004Applicant: ORBOTECH LTD.Inventors: Sharon Duvdevani, Tally Gilat-Bernshtein, Eyal Klingbell, Meir Mayo, Shmuel Rippa, Zeev Smilansky