Abstract: The debug system described in this patent specification provides a system that generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device. This particular FPGA device is called a Behavior Processor. This Behavior Processor executes in hardware those code constructs that were previously executed in software. When some condition is satisfied (e.g., If . . . then . . . else loop) which requires some intervention by the workstation or the software model, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response.

Abstract: The debug system described in this patent specification provides a system that generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device. This particular FPGA device is called a Behavior Processor. This Behavior Processor executes in hardware those code constructs that were previously executed in software. When some condition is satisfied (e.g., If . . . then . . . else loop) which requires some intervention by the workstation or the software model, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response.

Abstract: The debug system described in this patent specification provides a system that generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device. This particular FPGA device is called a Behavior Processor. This Behavior Processor executes in hardware those code constructs that were previously executed in software. When some condition is satisfied (e.g., If . . . then . . . else loop) which requires some intervention by the workstation or the software model, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response.

Abstract: The multi-user server technology allows multiple host stations to configure, load, and execute multiple jobs in a reconfigurable hardware unit for emulation purposes, simulation acceleration purposes, and a combination of emulation and simulation in a concurrent manner. The reconfigurable hardware unit includes a plurality of hardware resources (e.g., FPGA chips on slot module boards) for modeling at least a portion of one or more user design. The server includes a bus arbiter for deciding which one of the host stations will be coupled to the hardware resources via the bus multiplexer. The plurality of hardware resources includes slot modules, which includes one or more boards of FPGA chips. An arbitration decision is made to assign a particular slot(s) to a particular host. A host and its respective assigned slot(s) can communicate with each other while other hosts and their respective assigned slot(s) communicate with each other.

Abstract: The multi-user server technology allows multiple host stations to configure, load, and execute multiple jobs in a reconfigurable hardware unit for emulation purposes, simulation acceleration purposes, and a combination of emulation and simulation in a concurrent manner. The reconfigurable hardware unit includes a plurality of hardware resources (e.g., FPGA chips on slot module boards) for modeling at least a portion of one or more user designed. The server includes a bus arbiter for deciding which one of the host stations will be coupled to the hardware resources via the bus multiplexer. The plurality of hardware resources includes slot modules, which includes one or more boards of FPGA chips. An arbitration decision is made to assign a particular slot(s) to a particular host. A host and its respective assigned slot(s) can communicate with each other while other hosts and their respective assigned slot(s) communication with each other.

Abstract: A debug system generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device for used in electronic design automation (EDA). The FPGA device (Behavior Processor) operates to execute in hardware code constructs previously executed in software. When some condition is satisfied (e.g. If . . . then . . . else loop) requiring intervention, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response. A memory block from a logic device is mapped to a memory device in a re-configurable hardware unit using a memory mapping system including a conductive connector driver, a memory block interface, and evaluation logic in each logic device, the connector driver, the interface, and the connector controller, the evaluation logic providing control signals used to evaluate data in the hardware model and to control write/read memory access between the logic device and the memory device via the driver and interface.

Abstract: A high fan-out hub array system and method is provided. The system includes at least one hub that contains user logic that receive signals from various chips and boards, and which quickly turnarounds another signal (based on the logic) out to the desired chips and boards. In a CLKGEN implementation, a global clock is generated in the hub and distributed in a high fan-out manner to all the FPGA logic chips in the system. For a bus resolution application, a hub contains bus resolution logic to resolve bus access requests. It resolves the various requests and delivers the result to all the relevant chips and boards. In a STOPWHEN application, when a STOPWHEN condition has been met, the system delivers a pause signal to all the chips and boards via the high fan-out hubs.

Abstract: In a verification system, a dynamic logic evaluation system and method dynamically calculates the minimum evaluation time for each input. Thus, this system and method will remove the performance burden that a fixed and statically calculated evaluation time would introduce. By dynamically calculating different evaluation times based on the input, 99% of the inputs will not be delayed for the sake of 1% of the inputs that actually need the worst possible evaluation time. The dynamic logic evaluation system and method comprises a global control unit coupled to a propagation detector, where the propagation detector is placed in each FPGA chip. The propagation detector in the FPGA chip alerts the global control unit of any input data that is currently propagating within the FPGA chips. A master clock controls the operation of this dynamic evaluation system and method. As long as any input data is propagating, the global control unit will prevent the next input from being provided to the FPGA chips for evaluation.

Abstract: A high fan-out hub array system and method is provided. The system includes at least one hub that contains user logic that receive signals from various chips and boards, and which quickly turnarounds another signal (based on the logic) out to the desired chips and boards. In a CLKGEN implementation, a global clock is generated in the hub and distributed in a high fan-out manner to all the FPGA logic chips in the system. For a bus resolution application, a hub contains bus resolution logic to resolve bus access requests. It resolves the various requests and delivers the result to all the relevant chips and boards. In a STOPWHEN application, when a STOPWHEN condition has been met, the system delivers a pause signal to all the chips and boards via the high fan-out hubs.

Abstract: The FPGA array in the Simulation system is provided on the motherboard through a particular board interconnect structure to provide easy expandability and maximize packaging density with a single PCB design. Each chip may have up to eight sets of interconnections, where the interconnections are arranged according to adjacent direct-neighbor interconnects (i.e., N[73:0], S[73:0], W[73:0], E[73:0]), and one-hope neighbor interconnects (i.e., NH[27:0], SH[27:0], XH[36:0], XH[72:37]), excluding the local bus connections, within a single board and across different boards. Each chip is capable of being interconnected directly to adjacent neighbor chips, or in one hop to a non-adjacent chip located above, below, left, and right. In the X direction (east-west), the array is connected in a torus. In the Y direction (north-south), the array is connected in a column.

Abstract: The coverification system includes a reconfigurable computing system (hereinafter “RCC computing system”) and a reconfigurable computing hardware array (hereinafter “RCC hardware array”). In some embodiments, the target system and the external I/O devices are not necessary since they can be modeled in software. In other embodiments, the target system and the external I/O devices are actually coupled to the coverification system to obtain speed and use actual data, rather than simulated test bench data. The RCC computing system contains a CPU and memory for processing data for modeling the entire user design in software. The RCC computing system also contains clock logic (for clock edge detection and software clock generation), test bench processes for testing the user design, and device models for any I/O device that the user decides to model in software instead of using an actual physical I/O device.

Abstract: The SEmulation system provides four modes of operation: (1) Software Simulation, (2) Simulation via Hardware Acceleration, (3) In-Circuit Emulation (ICE), and (4) Post-Simulation Analysis. At a high level, the present invention may be embodied in each of the above four modes or various combinations of these modes. At the core of these modes is a software kernel which controls the overall operation of this system. The main control loop of the kernel executes the following steps: initialize system, evaluate active test-bench processes/components, evaluate clock components, detect clock edge, update registers and memories, propagate combinational components, advance simulation time, and continue the loop as long as active test-bench processes are present.

Abstract: The SEmulation system provides four modes of operation: (1) Software Simulation, (2) Simulation via Hardware Acceleration, (3) In-Circuit Emulation (ICE), and (4) Post-Simulation Analysis. At a high level, the present invention may be embodied in each of the above four modes or various combinations of these modes. At the core of these modes is a software kernel which controls the overall operation of this system. The main control loop of the kernel executes the following steps: initialize system, evaluate active test-bench processes/components, evaluate clock components, detect clock edge, update registers and memories, propagate combinational components, advance simulation time, and continue the loop as long as active test-bench processes are present.

Abstract: The SEmulation system provides four modes of operation: (1) Software Simulation, (2) Simulation via Hardware Acceleration, (3) In-Circuit Emulation (ICE), and (4) Post-Simulation Analysis. At a high level, the present invention may be embodied in each of the above four modes or various combinations of these modes. At the core of these modes is a software kernel which controls the overall operation of this system. The main control loop of the kernel executes the following steps: initialize system, evaluate active test-bench processes/components, evaluate clock components, detect clock edge, update registers and memories, propagate combinational components, advance simulation time, and continue the loop as long as active test-bench processes are present.