Abstract: A method for generating and updating position distribution graph comprises: generating a position distribution graph according to a circuit bitmap and an exposure pattern, performing an exposure simulation according to the position distribution graph to generate an exposure result graph, comparing the circuit bitmap with the exposure result graph to generate a plurality of error distribution candidate graphs, selecting one of the error distribution candidate graphs to serve as an error distribution graph, and performing a zero-one integer programming to update the position distribution graph according to the circuit bitmap and the error distribution graph, wherein the updated position distribution graph is associated with the error distribution graph.

Abstract: A memory page management method is provided. The method includes receiving a state-change notification corresponding to a state-change page, and grouping the state-change page from a list to which the state-change page belongs into a keep list or an adaptive LRU list of an adaptive adjusting list according to the state-change notification; receiving an access command from a CPU to perform an access operation to target page data corresponding to a target page; determining that a cache hit state is a hit state or a miss state according to a target NVM page address corresponding to the target page, and grouping the target page into the adaptive LRU list according to the cache hit state; and searching the adaptive page list according to the target NVM page address to obtain a target DRAM page address to complete the access command corresponding to the target page data.

Abstract: A method for generating and updating position distribution graph comprises: generating a position distribution graph according to a circuit bitmap and an exposure pattern, performing an exposure simulation according to the position distribution graph to generate an exposure result graph, comparing the circuit bitmap with the exposure result graph to generate a plurality of error distribution candidate graphs, selecting one of the error distribution candidate graphs to serve as an error distribution graph, and performing a zero-one integer programming to update the position distribution graph according to the circuit bitmap and the error distribution graph, wherein the updated position distribution graph is associated with the error distribution graph.

Abstract: A method for compensating a design image of a workpiece and a system for processing the design image of the workpiece are disclosed. The method includes the following steps. Obtaining a real image of the workpiece, with the real image having registration holes. Calculating a slope value for each of the registration holes. Determining an amount of interpolation points between each two neighboring registration holes of the registration holes according to the slope value corresponding to each of the registration holes. Obtaining positions of control points in blocks formed by the registration holes. Compensating the design image of the workpiece according to positions of the registration holes, positions of the plurality of interpolation points and the positions of the control points for generating a mapping image. Outputting the mapping image adapted to be mapped onto the workpiece. The system, together with the method, will be introduced.

Abstract: A method for compensating a design image of a workpiece and a system for processing the design image of the workpiece are disclosed. The method includes the following steps. Obtaining a real image of the workpiece, with the real image having registration holes. Calculating a slope value for each of the registration holes. Determining an amount of interpolation points between each two neighboring registration holes of the registration holes according to the slope value corresponding to each of the registration holes. Obtaining positions of control points in blocks formed by the registration holes. Compensating the design image of the workpiece according to positions of the registration holes, positions of the plurality of interpolation points and the positions of the control points for generating a mapping image. Outputting the mapping image adapted to be mapped onto the workpiece. The system, together with the method, will be introduced.

Abstract: A method and a system for digital direct imaging, an image generating method and an electronic device are provided. The method for digital direct imaging includes: obtaining a first image of a first format; converting the first image into a second image of a second format, wherein the second image includes a contour description; generating a correction parameter according to at least one mark on a substrate; correcting the second image according to the contour description and the correction parameter; and performing a rasterization operation on the corrected second image and imaging the second image processed by the rasterization operation on the substrate by an exposure device.

Abstract: An exposure apparatus including an optical device set and a substrate carrying platform is provided. The optical device set includes a plurality of light sources, at least one rotating beam deflector and at least one deflector set. The plurality of light sources are configured to emit a plurality of beams. Each deflector set includes a plurality of deflectors. The substrate carrying platform is configured to move an exposed substrate disposed on the substrate carrying platform relative to the optical device set along a relative movement direction. The plurality of beams sequentially travel through the at least one rotating beam deflector and the plurality of deflectors to be projected on the exposed substrate. Trajectories of the plurality of beams projected on the exposed substrate form a plurality of scan lines through rotation of the at least one rotating beam deflector.

Abstract: A memory page management method is provided. The method includes receiving a state-change notification corresponding to a state-change page, and grouping the state-change page from a list to which the state-change page belongs into a keep list or an adaptive LRU list of an adaptive adjusting list according to the state-change notification; receiving an access command from a CPU to perform an access operation to target page data corresponding to a target page; determining that a cache hit state is a hit state or a miss state according to a target NVM page address corresponding to the target page, and grouping the target page into the adaptive LRU list according to the cache hit state; and searching the adaptive page list according to the target NVM page address to obtain a target DRAM page address to complete the access command corresponding to the target page data.

Abstract: A method and a system for digital direct imaging, an image generating method and an electronic device are provided. The method for digital direct imaging includes: obtaining a first image of a first format; converting the first image into a second image of a second format, wherein the second image includes a contour description; generating a correction parameter according to at least one mark on a substrate; correcting the second image according to the contour description and the correction parameter; and performing a rasterization operation on the corrected second image and imaging the second image processed by the rasterization operation on the substrate by an exposure device.

Abstract: An exposing method adapted to a maskless photolithography process. The exposing method includes reading an exposure file; obtaining a plurality of coordinate information corresponding to a plurality of patterns contained in the exposure file, according to the exposure file; generating graphical data, according to the plurality of coordinate information; generating scanning data corresponding to each of a plurality of polygon mirrors or each of at least one polygon mirror group, according to the graphical data and a configuration of the polygon mirrors, wherein every two rotation directions of every two adjacent polygon mirrors of the plurality of polygon mirrors are different, or every two rotation directions of every two adjacent polygon mirrors of the at least one polygon mirror group are different.

Abstract: An exposing method adapted to a maskless photolithography process. The exposing method includes reading an exposure file; obtaining a plurality of coordinate information corresponding to a plurality of patterns contained in the exposure file, according to the exposure file; generating graphical data, according to the plurality of coordinate information; generating scanning data corresponding to each of a plurality of polygon mirrors or each of at least one polygon mirror group, according to the graphical data and a configuration of the polygon mirrors, wherein every two rotation directions of every two adjacent polygon mirrors of the plurality of polygon mirrors are different, or every two rotation directions of every two adjacent polygon mirrors of the at least one polygon mirror group are different.

Abstract: A data-processing apparatus and an operation method thereof are provided. The data-processing apparatus includes a tiling circuit and a post-stage processing circuit. The tiling circuit is configured to receive input data. The tiling circuit divides a current frame of the input data into at least one tile and checks a motion state of the current tile in the at least one tile. The post-stage processing circuit is coupled to the tiling circuit to receive the current tile. The post-stage processing circuit performs post processing on the current tile to generate a processed current tile of the current frame or to obtain a processed corresponding tile of a previous frame and serves it as the processed current tile of the current frame, according to the motion state of the current tile.

Abstract: A data-processing apparatus and an operation method thereof are provided. The data-processing apparatus includes a tiling circuit and a post-stage processing circuit. The tiling circuit is configured to receive input data. The tiling circuit divides a current frame of the input data into at least one tile and checks a motion state of the current tile in the at least one tile. The post-stage processing circuit is coupled to the tiling circuit to receive the current tile. The post-stage processing circuit performs post processing on the current tile to generate a processed current tile of the current frame or to obtain a processed corresponding tile of a previous frame and serves it as the processed current tile of the current frame, according to the motion state of the current tile.

Abstract: An exemplary embodiment describes a method for tile elimination, including: reading in data of a new tile; reading signature values corresponding to the new tile from a signature value repository; generating signature values for the new tile; comparing the read signature values and the generated signature values of the same tile to determine whether the two sets of signature values being identical; when the two sets of signature values being identical, copying the new tile directly from a tile frame buffer without rendering; otherwise, updating the signature value repository with the generated signature values replacing the stored signature values; rendering the tile; and updating the tile frame buffer with the newly rendered tile.

Abstract: An exemplary embodiment describes a method for tile elimination, including: reading in data of a new tile; reading signature values corresponding to the new tile from a signature value repository; generating signature values for the new tile; comparing the read signature values and the generated signature values of the same tile to determine whether the two sets of signature values being identical; when the two sets of signature values being identical, copying the new tile directly from a tile frame buffer without rendering; otherwise, updating the signature value repository with the generated signature values replacing the stored signature values; rendering the tile; and updating the tile frame buffer with the newly rendered tile.

Abstract: A method for hibernation mechanism and a computer system therefor are provided. The method includes the followings. An initial process of a hibernation mechanism is performed in a computer system, in which a non-swappable memory of a main memory is partitioned into a plurality of non-swappable segments, and each segment corresponds to a status value indicating whether the content of the segment has been changed. During a process of entering a hibernation state, for each non-swappable segment, it is determined whether the segment is to be written to a storage device according to the status value. The segment is written into the storage device when a determination result indicates the segment has been changed, or else the computer does not write the segment to the storage device when the determination result indicates the segment is has not been changed.

Abstract: An apparatus and a method for performing video decoding processes in parallel are provided. The method is adapted for utilizing a first cluster and a second cluster of a processor to perform the video data decoding process in parallel. The method includes performing a VLD process to the video data with the first cluster, so as to obtain a plurality of coefficients and then performing an IZ process, an IQ process, and an IDCT process to the coefficients with the second cluster, so as to obtain a plurality of pixels values of the video data. When the first cluster decodes a coefficient of the video data, the second cluster performs the IZ, IQ, and IDCT processes to a coefficient previously decoded by the second cluster of the video data. Accordingly, a parallel process is realized and the decoding speed is increased.

Abstract: Disclosed is a power aware method and apparatus of video decoder on a multi-core platform. The power aware apparatus comprises a power management unit, and a processor unit having an entropy decoder and a decoder. The processor unit has at least one voltage and at least one frequency. One processor of the multi-core platform performs the entropy decoding for a frame, collects the entropy decoded information, and computes the decompressing time. Based on the computed decompressing time, the processor sets up the voltage and frequency for other or all processors to reduce power consumption for video decoders.

Abstract: An apparatus and a method for performing video decoding processes in parallel are provided. The method is adapted for utilizing a first cluster and a second cluster of a processor to perform the video data decoding process in parallel. The method includes performing a VLD process to the video data with the first cluster, so as to obtain a plurality of coefficients and then performing an IZ process, an IQ process, and an IDCT process to the coefficients with the second cluster, so as to obtain a plurality of pixels values of the video data. When the first cluster decodes a coefficient of the video data, the second cluster performs the IZ, IQ, and IDCT processes to a coefficient previously decoded by the second cluster of the video data. Accordingly, a parallel process is realized and the decoding speed is increased.

Abstract: Disclosed is a power aware method and apparatus of video decoder on a multi-core platform. The power aware apparatus comprises a power management unit, and a processor unit having an entropy decoder and a decoder. The processor unit has at least one voltage and at least one frequency. One processor of the multi-core platform performs the entropy decoding for a frame, collects the entropy decoded information, and computes the decompressing time. Based on the computed decompressing time, the processor sets up the voltage and frequency for other or all processors. This invention of the power aware method and apparatus reduces power consumption for video decoders.