Patents by Inventor Shaungchen Li

Shaungchen Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DPU architecture
    Patent number: 10242728
    Abstract: A dynamic random access memory (DRAM) processing unit (DPU) may include at least one computing cell array having a plurality of DRAM-based computing cells arranged in an array having at least one column in which the at least one column may include at least three rows of DRAM-based computing cells configured to provide a logic function that operates on a first and a second row of the at least three rows and configured to store a result of the logic function in a third row of the at least three rows; and a controller that may be coupled to the at least one computing cell array to configure the at least one computing cell array to perform a DPU operation.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: March 26, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shaungchen Li, Dimin Niu, Krishna Malladi, Hongzhong Zheng
  • Software stack and programming for DPU operations
    Patent number: 10180808
    Abstract: A system includes a library, a compiler, a driver and at least one dynamic random access memory (DRAM) processing unit (DPU). The library may determine at least one DPU operation corresponding to a received command. The compiler may form at least one DPU instruction for the DPU operation. The driver may send the at least one DPU instruction to at least one DPU. The DPU may include at least one computing cell array that includes a plurality of DRAM-based computing cells arranged in an array having at least one column in which the at least one column may include at least three rows of DRAM-based computing cells configured to provide a logic function that operates on a first row and a second row of the at least three rows and configured to store a result of the logic function in a third row of the at least three rows.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: January 15, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shaungchen Li, Dimin Niu, Krishna Malladi, Hongzhong Zheng
  • DPU ARCHITECTURE
    Publication number: 20180122456
    Abstract: A dynamic random access memory (DRAM) processing unit (DPU) may include at least one computing cell array having a plurality of DRAM-based computing cells arranged in an array having at least one column in which the at least one column may include at least three rows of DRAM-based computing cells configured to provide a logic function that operates on a first and a second row of the at least three rows and configured to store a result of the logic function in a third row of the at least three rows; and a controller that may be coupled to the at least one computing cell array to configure the at least one computing cell array to perform a DPU operation.
    Type: Application
    Filed: February 6, 2017
    Publication date: May 3, 2018
    Inventors: Shaungchen LI, Dimin NIU, Krishna MALLADI, Hongzhong ZHENG
  • SOFTWARE STACK AND PROGRAMMING FOR DPU OPERATIONS
    Publication number: 20180121130
    Abstract: A system includes a library, a compiler, a driver and at least one dynamic random access memory (DRAM) processing unit (DPU). The library may determine at least one DPU operation corresponding to a received command. The compiler may form at least one DPU instruction for the DPU operation. The driver may send the at least one DPU instruction to at least one DPU. The DPU may include at least one computing cell array that includes a plurality of DRAM-based computing cells arranged in an array having at least one column in which the at least one column may include at least three rows of DRAM-based computing cells configured to provide a logic function that operates on a first row and a second row of the at least three rows and configured to store a result of the logic function in a third row of the at least three rows.
    Type: Application
    Filed: February 6, 2017
    Publication date: May 3, 2018
    Inventors: Shaungchen LI, Dimin NIU, Krishna MALLADI, Hongzhong ZHENG
  • Circuits and micro-architecture for a DRAM-based processing unit
    Patent number: 9922696
    Abstract: A dynamic random access memory (DRAM) processing unit (DPU) may include at least one computing cell array that may include a plurality of DRAM-based computing cells arranged in an array having at least one column in which the at least one column may include at least three rows of DRAM-based computing cells configured to provide a logic function that operates on a first row and a second row of the at least three rows and configured to store a result of the logic function in a third row of the at least three rows.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: March 20, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shaungchen Li, Dimin Niu, Krishna Malladi, Hongzhong Zheng