Abstract: Plasma charging devices and methods are disclosed for detecting plasma charging during semiconductor wafer processing. Charging monitors are disclosed having ferroelectric capacitance elements which can be preprogrammed prior to processing steps of interest, and then subsequently measured afterwards, in order to determine whether plasma related charging is a problem in the intervening processing steps.

Abstract: A charge monitoring device comprising one or more capacitor-resistor pairs. The one or more capacitor-resistor pairs comprise a resistor and a capacitor connected in series. The capacitor comprises a ferroelectric charge storage layer. A method of forming the charge storage device is also provided. The charge monitoring device may be used to measure charge accumulation on a semiconductor wafer. The method comprises the steps of positioning a charge monitoring device in a semiconductor wafer production chamber, initiating a manufacturing process in the chamber and measuring the charge accumulation on the charge monitoring device.

Abstract: Charging damage, caused by electron shading during plasma etching in a dual damascene structure, is alleviated by first depositing a protective conductive layer which provides a conductive path for maintaining charge balance in the etched structures. This conductive layer reduces the buildup of unbalanced positive charge in the contact opening, and the damage done to underlying layers caused by the resultant tunneling current. Further, if the protective conductive layer comprises a material which can also serve as an interdiffusion barrier layer for the contact opening fill material, a separate subsequent step to deposit such a barrier layer on the contact opening sidewall is avoided. Further, in the process of doing lithography on the trench etch resist layer, the protective conductive layer also functions as an antireflective coating, permitting the stepper to accurately focus the desired pattern.

Abstract: Plasma charging devices and methods are disclosed for detecting plasma charging during semiconductor wafer processing. Charging monitors are disclosed having ferroelectric capacitance elements which can be preprogrammed prior to processing steps of interest, and then subsequently measured afterwards, in order to determine whether plasma related charging is a problem in the intervening processing steps.

Abstract: Charging damage, caused by electron shading during plasma etching in a dual damascene structure, is alleviated by first depositing a protective conductive layer which provides a conductive path for maintaining charge balance in the etched structures. This conductive layer reduces the buildup of unbalanced positive charge in the contact opening, and the damage done to underlying layers caused by the resultant tunneling current. Further, if the protective conductive layer comprises a material which can also serve as an interdiffusion barrier layer for the contact opening fill material, a separate subsequent step to deposit such a barrier layer on the contact opening sidewall is avoided. Further, in the process of doing lithography on the trench etch resist layer, the protective conductive layer also functions as an antireflective coating, permitting the stepper to accurately focus the desired pattern.

Abstract: Methods and apparatuses for reducing electrical arcing currents or electron emissions to a wafer or to components in a plasma chamber are provided. An insert for use in a process chamber having a wafer support is disclosed. The insert comprises a composite member formed of a first material, such as for example, silicon, and a second material, such as for example, SiO2, having a greater electrical impedance than the first material. The composite member has a surface which is adapted to be disposed adjacent to the wafer support, and which is made of the second material. In one aspect, the process chamber further has an outer member adapted to surround the wafer support. The composite member has a surface which is adapted to be disposed adjacent to the outer member and which is made of the second material. In another aspect, the composite member has a surface which is adapted to be disposed adjacent to a semiconductor wafer and which is made of the second material.

Abstract: Plasma charging devices and methods are disclosed for detecting plasma charging during semiconductor wafer processing. Charging monitors are disclosed having ferroelectric capacitance elements which can be preprogrammed prior to processing steps of interest, and then subsequently measured afterwards, in order to determine whether plasma related charging is a problem in the intervening processing steps.

Abstract: A plasma chamber apparatus and method having a process kit capable of reducing or eliminating electrical arcing from exposed metal at the perimeter of a workpiece. The plasma chamber includes a cathode electrode adjacent the workpiece. A process kit encircles the perimeter of the workpiece. The process kit includes a dielectric shield and an electrically conductive collar that overlies the dielectric shield. The resistivity of the conductive collar is 0.1 ohm-cm or less.

Abstract: An embodiment of the instant invention is a method of fabricating a ferroelectric capacitor which is situated over a structure, the method comprising the steps of: forming a bottom electrode on the structure (124 of FIG. 1), the bottom electrode having a top surface and sides; forming a capacitor dielectric (126 of FIG. 1) comprised of a ferroelectric material on the bottom electrode, the capacitor dielectric having a top surface and sides; forming a top electrode (128 and 130 of FIG. 1) on the capacitor dielectric, the top electrode having a top surface and sides, the ferroelectric capacitor is comprised of the bottom electrode, the capacitor dielectric, and the top electrode; forming a barrier layer (118 and 120 of FIG.

Abstract: An embodiment of the instant invention is a method of forming a conductive contact to a top electrode (308 and 310 of FIG. 4d) of a ferroelectric capacitor comprised of a bottom electrode (304 of FIG. 4d) situated under the top electrode and a ferroelectric material (306 of FIG. 4d) situated between the top electrode and the bottom electrode, the method comprising the steps of: forming a layer (408 or 312 of FIG. 4) over the top electrode; forming an opening (414 of FIG. 4d) in the layer to expose a portion of the top electrode by etching the opening into the layer using a hydrogen-free etchant; and depositing conductive material (432 of FIG. 4d) in the opening to form an electrical connection with the top electrode.

Abstract: An apparatus, system and method for the real-time monitoring of plasma charging during plasma processing are provided which overcome the deficiencies in currently available apparatus, systems and methods. According to one embodiment, the method and apparatus utilizes a detection wafer that comprises an Al pad located on the wafer and placed in contact with the plasma. The potential difference generated between the Al pad and a substrate as a result of plasma processing is the plasma charging voltage Vc. The potential difference is transmitted through electrical contacts located in a modified biased lift pin assembly supporting the detection wafer, and in the detection wafer itself, at locations remote from the plasma. Electrical contact with the detection wafer is thus established by positive physical contact from the biased lift pins and the potential difference is registered on apparatus external to the processing chamber and connected to the electrical contacts located remotely from the plasma.

Abstract: A plasma chamber apparatus and method having a process kit capable of reducing or eliminating electrical arcing from exposed metal at the perimeter of a workpiece. The plasma chamber includes a cathode electrode adjacent the workpiece. A process kit encircles the perimeter of the workpiece. The process kit includes a dielectric shield and an electrically conductive collar that overlies the dielectric shield. The resistivity of the conductive collar is 0.1 ohm-cm or less.

Abstract: An array of active pixel sensors includes a substrate. An interconnect structure is formed adjacent to the substrate. The interconnect structure includes a plurality of conductive vias. A plurality of photo sensors are formed adjacent to the interconnect structure. Each photo sensor includes a pixel electrode. Each pixel electrode is electrically connected to the substrate through a corresponding conductive yet. A I-layer is formed over each of the pixel electrodes. The array of active pixel sensors further includes a conductive mesh formed adjacent to the photo sensors. An inner surface of the conductive mesh is electrically and physically connected to the photo sensors, and electrically connected to the substrate through a conductive via. The conductive mesh providing light shielding between photo sensors thereby reducing cross-talk between the photo sensors. The conductive mesh includes apertures that align with at least one of the pixel electrodes of the photo sensors.

Abstract: An embodiment of the instant invention is a method of forming a conductive contact to a top electrode (308 and 310 of FIG. 4d) of a ferroelectric capacitor comprised of a bottom electrode (304 of FIG. 4d) situated under the top electrode and a ferroelectric material (306 of FIG. 4d) situated between the top electrode and the bottom electrode, the method comprising the steps of: forming a layer (408 or 312 of FIG. 4) over the top electrode; forming an opening (414 of FIG. 4d) in the layer to expose a portion of the top electrode by etching the opening into the layer using a hydrogen-free etchant; and depositing conductive material (432 of FIG. 4d) in the opening to form an electrical connection with the top electrode.

Abstract: A capacitor structure or an array of capacitors and a method of fabricating the structure utilize the contours of a cavity created in a layer stack to form two three-dimensional electrode plates. The three-dimensional electrode plates reduce the lateral size of the capacitor structure. The fabrication of the capacitor structure is compatible to conventional CMOS processing technology, in which the resulting capacitor structure may become embedded in a CMOS device. As an example, the capacitor structure may be fabricated along with a MOS transistor to produce a one-transistor-one-capacitor nonvolatile memory cell. Preferably, the three-dimensional electrode plates are made of platinum (Pt) or iridium (Ir) and the capacitor dielectric is a ferrous-electric material, such as lead-zirconate-titanate (PZT) or barium-strontium-titanate (BST).

Abstract: An ink jet nozzle. The ink jet nozzle includes a substrate having an upper surface in which an ink energizing element is attached to the upper surface of the substrate. The ink jet nozzle further includes an oxide-nitride or oxide-carbide composite orifice layer. The oxide-nitride composite orifice layer includes a lower surface conformally connected to the upper surface of the substrate, and an exterior surface facing away from the substrate. The oxide-nitride composite orifice layer defines a firing chamber. The firing chamber opens through a nozzle aperture in the exterior surface, and extends downward with a negative slope through the oxide-nitride orifice layer to expose the ink energizing element.

Abstract: An image pixel sensor array. The image pixel sensor array includes a substrate. An interconnect structure is formed adjacent to the substrate. A plurality of image pixel sensors are formed adjacent to the interconnect structure. Each image pixel sensor includes a pixel electrode, and an I-layer formed adjacent to the pixel electrode. The I-layer includes a first surface adjacent to the pixel electrode, and a second surface opposite the first surface. The first surface includes a first surface area which is less than a second surface area of the second surface. The image pixel sensor array further includes an insulating material between each image pixel sensor, and a transparent electrode formed over the image pixel sensors. The transparent electrode electrically connects the image pixel sensors and the interconnect structure.

Abstract: An ink jet nozzle. The ink jet nozzle includes a substrate having an upper surface in which an ink energizing element is attached to the upper surface of the substrate. The ink jet nozzle further includes an oxide-nitride or oxide-carbide composite orifice layer. The oxide-nitride composite orifice layer includes a lower surface conformally connected to the upper surface of the substrate, and an exterior surface facing away from the substrate. The oxide-nitride composite orifice layer defines a firing chamber. The firing chamber opens through a nozzle aperture in the exterior surface, and extends downward with a negative slope through the oxide-nitride orifice layer to expose the ink energizing element.

Abstract: An active pixel sensor. The active pixel sensor includes a substrate, an interconnect structure adjacent to the substrate, and at least one photo sensor adjacent to the interconnect structure. At least one photo sensor is formed adjacent to the interconnect structure. Each photo sensor includes a pixel electrode which includes a patterned doped semiconductor layer. An I-layer is formed adjacent to the patterned doped semiconductor layer. A transparent electrode is formed adjacent to the I-layer. A method of forming the active pixel sensor includes forming an interconnect structure over a substrate. Next, a doped semiconductor layer is deposited over the interconnect structure. The doped semiconductor layer is etched forming pixel electrode. An I-layer is deposited over the pixel electrodes. Finally, a transparent conductive layer is deposited over the I-layer.

Abstract: An active pixel sensor. The active pixel sensor includes a substrate, an interconnect structure adjacent to the substrate, and at least one photo sensor adjacent to the interconnect structure. Each photo sensor includes an individual pixel electrode. An I-layer is formed over all of the pixel electrodes. A transparent electrode is formed over the I-layer. An inner surface of the transparent electrode is electrically connected to the I-layer and the interconnect structure.