Patents by Inventor Shawn D Burnham
Shawn D Burnham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9929243Abstract: A method of making a stepped field gate for an FET including forming a first passivation layer on a barrier layer, defining a first field plate by using electron beam (EB) lithography and by depositing a first negative EB resist, forming a second passivation layer over first negative EB resist and the first passivation layer, planarizing the first negative EB resist and the second passivation layer, defining a second field plate by using EB lithography and by depositing a second negative EB resist connected to the first negative EB resist, forming a third passivation layer over second negative EB resist and the second passivation layer, planarizing the second negative EB resist and the third passivation layer, removing the first and second negative EB resist, and forming a stepped field gate by using lithography and plating in a void left by the removed first and second negative EB resist.Type: GrantFiled: August 3, 2015Date of Patent: March 27, 2018Assignee: HRL Laboratories, LLCInventors: Andrea Corrion, Keisuke Shinohara, Miroslav Micovic, Rongming Chu, David F. Brown, Alexandros D. Margomenos, Shawn D. Burnham
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Patent number: 9252247Abstract: The interface resistance between the source/drain and gate of an HFET may be significantly reduced by engineering the bandgap of the 2DEG outside a gate region such that the charge density is substantially increased. The resistance may be further reduced by using an n+GaN Cap layer over the channel layer and barrier layer such that a horizontal surface of the barrier layer beyond the gate region is covered by the n+GaN Cap layer. This technique is applicable to depletion and enhancement mode HFETs.Type: GrantFiled: January 10, 2014Date of Patent: February 2, 2016Assignee: HRL Laboratories, LLCInventors: Miroslav Micovic, Andrea Corrion, Keisuke Shinohara, Peter J Willadsen, Shawn D Burnham, Hooman Kazemi, Paul B Hashimoto
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Patent number: 9190534Abstract: A method of fabricating a normally “off” GaN heterostructure field effect transistor having a source and a drain including depositing a passivation layer patterned to cover a channel region between a source and a drain, forming a first opening in the passivation layer, the first opening for defining a gate area in the channel region and the first opening having a first length dimension along a direction of current flow between the source and the drain, and implanting ions in an implant area within the gate area, wherein the implant area has a second length dimension along the direction of current flow shorter than the first length dimension.Type: GrantFiled: April 9, 2014Date of Patent: November 17, 2015Assignee: HRL Laboratories, LLCInventors: Tahir Hussain, Miroslav Micovic, Wah S. Wong, Shawn D. Burnham
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Patent number: 9142626Abstract: A method of making a stepped field gate for an FET including forming a first passivation layer on a barrier layer, defining a first field plate by using electron beam (EB) lithography and by depositing a first negative EB resist, forming a second passivation layer over first negative EB resist and the first passivation layer, planarizing the first negative EB resist and the second passivation layer, defining a second field plate by using EB lithography and by depositing a second negative EB resist connected to the first negative EB resist, forming a third passivation layer over second negative EB resist and the second passivation layer, planarizing the second negative EB resist and the third passivation layer, removing the first and second negative EB resist, and forming a stepped field gate by using lithography and plating in a void left by the removed first and second negative EB resist.Type: GrantFiled: August 30, 2013Date of Patent: September 22, 2015Assignee: HRL Laboratories, LLCInventors: Andrea Corrion, Keisuke Shinohara, Miroslav Micovic, Rongming Chu, David F. Brown, Alexandros D. Margomenos, Shawn D. Burnham
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Patent number: 8766321Abstract: A method of fabricating a GaN HEMT includes growing a first epitaxial layer on a substrate, growing a second epitaxial layer on the first epitaxial layer, growing a third epitaxial layer on the second epitaxial layer, depositing a first dielectric film on the third epitaxial layer, using dielectric films to form a first sidewall dielectric spacer, forming a sidewall gate adjacent the first sidewall dielectric spacer. The sidewall gate may be made to be less than 50 nm in length.Type: GrantFiled: December 28, 2012Date of Patent: July 1, 2014Assignee: HRL Laboratories, LLCInventors: Keisuke Shinohara, Andrea Corrion, Miroslav Micovic, Paul B. Hashimoto, Shawn D. Burnham, Hooman Kazemi, Peter J. Willadsen, Dean C. Regan
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Patent number: 8748244Abstract: The present invention relates to fabrication of enhancement mode and depletion mode High Electron Mobility Field Effect Transistors on the same die separated by as little as 10 nm. The fabrication method uses selective decomposition and selective regrowth of the Barrier layer and the Cap layer to engineer the bandgap of a region on a die to form an enhancement mode region. In these regions zero or more devices may be fabricated.Type: GrantFiled: April 26, 2012Date of Patent: June 10, 2014Assignee: HRL Laboratories, LLCInventors: Andrea Corrion, Miroslav Micovic, Keisuke Shinohara, Peter J Willadsen, Shawn D Burnham, Hooman Kazemi, Paul B Hashimoto
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Patent number: 8728884Abstract: A method of fabricating a normally “off” GaN heterostructure field effect transistor having a source and a drain including depositing a passivation layer patterned to cover a channel region between a source and a drain, forming a first opening in the passivation layer, the first opening for defining a gate area in the channel region and the first opening having a first length dimension along a direction of current flow between the source and the drain, and implanting ions in an implant area within the gate area, wherein the implant area has a second length dimension along the direction of current flow shorter than the first length dimension.Type: GrantFiled: July 28, 2009Date of Patent: May 20, 2014Assignee: HRL Laboratories, LLCInventors: Tahir Hussain, Miroslav Micovic, Wah S. Wong, Shawn D. Burnham
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Patent number: 8686473Abstract: The interface resistance between the source/drain and gate of an HFET may be significantly reduced by engineering the bandgap of the 2DEG outside a gate region such that the charge density is substantially increased. The resistance may be further reduced by using an n+GaN Cap layer over the channel layer and barrier layer such that a horizontal surface of the barrier layer beyond the gate region is covered by the n+GaN Cap layer. This technique is applicable to depletion and enhancement mode HFETs.Type: GrantFiled: June 2, 2010Date of Patent: April 1, 2014Assignee: HRL Laboratories, LLCInventors: Miroslav Micovic, Andrea Corrion, Keisuke Shinohara, Peter J Willadsen, Shawn D Burnham, Hooman Kazemi, Paul B Hashimoto
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Patent number: 8653559Abstract: A field effect transistor (FET) includes source and drain electrodes, a channel layer, a barrier layer over the channel layer, a passivation layer covering the barrier layer for passivating the barrier layer, a gate electrode extending through the barrier layer and the passivation layer, and a gate dielectric surrounding a portion of the gate electrode that extends through the barrier layer and the passivation layer, wherein the passivation layer is a first material and the gate dielectric is a second material, and the first material is different than the second material.Type: GrantFiled: June 29, 2011Date of Patent: February 18, 2014Assignee: HRL Laboratories, LLCInventors: Andrea Corrion, Karim S. Boutros, Mary Y. Chen, Samuel J. Kim, Rongming Chu, Shawn D. Burnham
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Publication number: 20130328061Abstract: A normally-off transistor includes a channel layer, an electron supply layer overlaying the channel layer, a source electrode and a drain electrode on the electron supply layer, an area in the electrode supply layer between the source electrode and the drain electrode treated with a fluoride based plasma followed by a chlorine based plasma treatment, a gate insulator overlaying the area, and a gate electrode overlaying the gate insulator.Type: ApplicationFiled: September 6, 2012Publication date: December 12, 2013Applicant: HRL LABORATORIES, LLC.Inventors: Rongming Chu, Brian Hughes, Andrea Corrion, Shawn D. Burnham, Karim S. Boutros
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Patent number: 8383471Abstract: A method of fabricating a GaN HEMT includes growing a first epitaxial layer on a substrate, growing a second epitaxial layer on the first epitaxial layer, growing a third epitaxial layer on the second epitaxial layer, depositing a first dielectric film on the third epitaxial layer, using dielectric films to form a first sidewall dielectric spacer, forming a sidewall gate adjacent the first sidewall dielectric spacer. The sidewall gate may be made to be less than 50 nm in length.Type: GrantFiled: April 11, 2011Date of Patent: February 26, 2013Assignee: HRL Laboratories, LLCInventors: Keisuke Shinihara, Andrea Corrion, Miroslav Micovic, Paul B. Hashimoto, Shawn D. Burnham, Hooman Kazemi, Peter J. Willadsen, Dean C. Regan
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Publication number: 20130001646Abstract: A field effect transistor (FET) includes source and drain electrodes, a channel layer, a barrier layer over the channel layer, a passivation layer covering the barrier layer for passivating the barrier layer, a gate electrode extending through the barrier layer and the passivation layer, and a gate dielectric surrounding a portion of the gate electrode that extends through the barrier layer and the passivation layer, wherein the passivation layer is a first material and the gate dielectric is a second material, and the first material is different than the second material.Type: ApplicationFiled: June 29, 2011Publication date: January 3, 2013Applicant: HRL LABORATORIES, LLCInventors: Andrea Corrion, Karim S. Boutros, Mary Y. Chen, Samuel J. Kim, Rongming Chu, Shawn D. Burnham
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Patent number: 8124505Abstract: A two stage plasma etching technique is described that allows the fabrication of an enhancement mode GaN HFET/HEMT. A gate recess area is formed in the Aluminum Gallium Nitride barrier layer of an GaN HFET/HEMT. The gate recess is formed by a two stage etching process. The first stage of the technique uses oxygen to oxidize the surface of the Aluminum Gallium Nitride barrier layer below the gate. Then the second stage uses Boron tricloride to remove the oxidized layer. The result is a self limiting etch process that uniformly thins the Aluminum Gallium Nitride layer below the HFET's gate region such that the two dimensional electron gas is not formed below the gate, thus creating an enhancement mode HFET.Type: GrantFiled: October 21, 2010Date of Patent: February 28, 2012Assignee: HRL Laboratories, LLCInventors: Shawn D Burnham, Karim S. Boutros