Abstract: A memory controller method and apparatus wherein data to be written to a memory device is stored in a data queue, the data queue has a plurality of entries wherein at least two of the entries are combined to store a single datum, the single datum is wider than a single entry of the entries and addresses associated with the stored data of the data queue are stored in an address queue, thereby providing a circular write buffer. Specific memory modules of a plurality of memory modules to be refreshed are indicated to a refresh controller to thereby selectively control which of the memory modules are refreshed by the refresh controller. Access is controlled to the plurality of memory modules, each of the memory modules having an associated type. Configuration status information indicating the associated type for each of the memory modules is stored so that, if an access operation is performed to a wrong type, uncorrectable error faults are generated and can be detected.