Abstract: The present disclosure includes apparatuses and methods related to microcode instructions indicating instruction types. One example apparatus comprises a memory storing a set of microcode instructions. Each microcode instruction of the set can comprise a first field comprising a number of control data units, and a second field comprising a number of type select data units. Each microcode instruction of the set can have a particular instruction type defined by a value of the number of type select data units, and particular functions corresponding to the number of control data units are variable based on the particular instruction type.

Abstract: The present disclosure includes apparatuses and methods related to microcode instructions indicating instruction types. One example apparatus comprises a memory storing a set of microcode instructions. Each microcode instruction of the set can comprise a first field comprising a number of control data units, and a second field comprising a number of type select data units. Each microcode instruction of the set can have a particular instruction type defined by a value of the number of type select data units, and particular functions corresponding to the number of control data units are variable based on the particular instruction type.

Abstract: Apparatus and methods for debugging on a host and memory device include an example apparatus comprising a memory device having an array of memory cells. Sensing circuitry is coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to perform logical operations on the memory device. A controller is coupled to the array and sensing circuitry, the controller is configured to control performance of the logical operations. An interface is configured to receive a debugging indication and to cause the controller to halt a logical operation on the memory device.

Abstract: The present disclosure includes apparatuses and methods related to microcode instructions. One example apparatus comprises a memory storing a set of microcode instructions. Each microcode instruction of the set can comprise a first field comprising a number of control data units, and a second field comprising a number of type select data units. Each microcode instruction of the set can have a particular instruction type defined by a value of the number of type select data units, and particular functions corresponding to the number of control data units are variable based on the particular instruction type.

Abstract: The present disclosure includes apparatus and methods for debugging on a host and memory device. An example apparatus comprises a memory device having an array of memory cells. Sensing circuitry is coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to perform logical operations on the memory device. A controller is coupled to the array and sensing circuitry to control performance of the logical operations. An interface is configured to receive a debugging indication and to cause the controller to halt a logical operation on the memory device.

Abstract: The present disclosure includes apparatus and methods for debugging on a memory device. An example apparatus comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to perform logical operations on the memory device. A controller is coupled to the array and sensing circuitry and configured to cause the memory device to store debugging code in the array of memory cells and execute instructions to perform logical operations using the sensing circuitry. The controller is further configured to receive an indication in the executing instructions to halt a logical operation, and to execute the debugging code on the memory device.

Abstract: The present disclosure includes apparatuses and methods related to microcode instructions. One example apparatus comprises a memory storing a set of microcode instructions. Each microcode instruction of the set can comprise a first field comprising a number of control data units, and a second field comprising a number of type select data units. Each microcode instruction of the set can have a particular instruction type defined by a value of the number of type select data units, and particular functions corresponding to the number of control data units are variable based on the particular instruction type.

Abstract: The present disclosure includes apparatuses and methods related to microcode instructions. One example apparatus comprises a memory storing a set of microcode instructions. Each microcode instruction of the set can comprise a first field comprising a number of control data units, and a second field comprising a number of type select data units. Each microcode instruction of the set can have a particular instruction type defined by a value of the number of type select data units, and particular functions corresponding to the number of control data units are variable based on the particular instruction type.

Abstract: The present disclosure includes apparatus and methods for debugging on a host and memory device. An example apparatus comprises a memory device having an array of memory cells. Sensing circuitry is coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to perform logical operations on the memory device. A controller is coupled to the array and sensing circuitry to control performance of the logical operations. An interface is configured to receive a debugging indication and to cause the controller to halt a logical operation on the memory device.

Abstract: The present disclosure includes apparatus and methods for debugging on a memory device. An example apparatus comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to perform logical operations on the memory device. A controller is coupled to the array and sensing circuitry and configured to cause the memory device to store debugging code in the array of memory cells and execute instructions to perform logical operations using the sensing circuity. The controller is further configured to receive an indication in the executing instructions to halt a logical operation, and to execute the debugging code on the memory device.

Abstract: The present disclosure includes apparatus and methods for debugging on a memory device. An example apparatus comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to perform logical operations on the memory device. A controller is coupled to the array and sensing circuitry and configured to cause the memory device to store debugging code in the array of memory cells and execute instructions to perform logical operations using the sensing circuitry. The controller is further configured to receive an indication in the executing instructions to halt a logical operation, and to execute the debugging code on the memory device.

Abstract: The present disclosure includes apparatuses and methods related to microcode instructions. One example apparatus comprises a memory storing a set of microcode instructions. Each microcode instruction of the set can comprise a first field comprising a number of control data units, and a second field comprising a number of type select data units. Each microcode instruction of the set can have a particular instruction type defined by a value of the number of type select data units, and particular functions corresponding to the number of control data units are variable based on the particular instruction type.

Abstract: The present disclosure includes apparatus and methods for debugging on a memory device. An example apparatus comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to perform logical operations on the memory device. A controller is coupled to the array and sensing circuitry and configured to cause the memory device to store debugging code in the array of memory cells and execute instructions to perform logical operations using the sensing circuitry. The controller is further configured to receive an indication in the executing instructions to halt a logical operation, and to execute the debugging code on the memory device.

Abstract: The present disclosure includes apparatus and methods for debugging on a host and memory device. An example apparatus comprises a memory device having an array of memory cells. Sensing circuitry is coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to perform logical operations on the memory device. A controller is coupled to the array and sensing circuitry to control performance of the logical operations. An interface is configured to receive a debugging indication and to cause the controller to halt a logical operation on the memory device.

Abstract: An image processing system includes at least one processor having a plurality of PCI Express channels and at least two application specific integrated circuits. The application specific integrated circuits are communicatively coupled to the at least one processor by a first of the plurality of PCI Express channels and a second of the plurality of PCI Express channels. Multiple threads of execution are split between the at least two application specific integrated circuits.

Abstract: An image processing system includes at least one processor having a plurality of PCI Express channels and at least two application specific integrated circuits. The application specific integrated circuits are communicatively coupled to the at least one processor by a first of the plurality of PCI Express channels and a second of the plurality of PCI Express channels. Multiple threads of execution are split between the at least two application specific integrated circuits.

Abstract: A preferred printing system includes a printer configured to communicatively couple with a workstation, which incorporates a first code entry device for receiving first coding information from a user. The printer incorporates a second code entry device that is configured to receive second coding information from the user. Additionally, the printer is configured to print data in response to correlating the first coding information received at the first code entry device with the second coding information received at the second code entry device. Devices, methods and computer readable media also are provided.

Abstract: A preferred printing system includes a printer configured to communicatively couple with a workstation, which incorporates a first code entry device for receiving first coding information from a user. The printer incorporates a second code entry device that is configured to receive second coding information from the user. Additionally, the printer is configured to print data in response to correlating the first coding information received at the first code entry device with the second coding information received at the second code entry device. Devices, methods and computer readable media also are provided.