Patents by Inventor Shawn Walker

Shawn Walker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170007790
    Abstract: A system and method for periodically providing air pressure through an air line coupled to an air cuff in order to purge unwanted moisture from the air line while maintaining pressure in the air cuff. An air pressure measurement device is coupled to the air line by means of pneumatic circuit and determines whether the air pressure in the air line and coupled air cuff is equal to, greater than or less than a preprogrammed air pressure value. A pressure regulator receives the air measurement signal and is configured to control an air pressure device to increase or decrease the air pressure in the air line based upon the measured air pressure. A purge regulator controls the air pressure device to periodically cause the air pressure device to increase the air pressure in the air line to a predetermined level for a predetermined period of time at predetermined intervals in order to rid the air line of any accumulated moisture.
    Type: Application
    Filed: June 29, 2016
    Publication date: January 12, 2017
    Inventor: Shawn Walker
  • Publication number: 20160016906
    Abstract: Provided are omecamtiv mecarbil dihydrochloride salt forms, compositions and pharmaceutical formulations thereof, and methods for their preparation and use.
    Type: Application
    Filed: March 14, 2014
    Publication date: January 21, 2016
    Applicants: AMGEN INC., CYTOKINETICS, INC.
    Inventors: Sheng Cui, Henry Morrison, Karthik Nagapudi, Shawn Walker, Charles Bernard, Karl Bennett Hansen, Neil Fred Langille, Alan Martin Allgeier, Steven Mennen, Jacqueline Woo, Bradley Paul Morgan, Alex Muci
  • Patent number: 7543113
    Abstract: A cache memory system capable of adaptively accommodating various memory line sizes comprises cache memory and cache logic. The cache memory has sets of ways. The cache logic is configured to request a memory line in response to a cache miss, and the memory line represents a portion of a way line. The cache logic is configured to select one of the ways based on which portion of the way line is represented by the memory line. The cache logic is further configured to store the memory line in the selected way.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: June 2, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Shawn Walker, Donald C. Soltis, Jr., Karl Brummel
  • Publication number: 20070067602
    Abstract: Systems, methodologies, media, and other embodiments associated with mitigating the effects of context switch cache and TLB misses are described. One exemplary system embodiment includes a processor configured to run a multiprocessing, virtual memory operating system. The processor may be operably connected to a memory and may include a cache and a translation lookaside buffer (TLB) configured to store TLB entries. The exemplary system may include a context control logic configured to selectively copy data from the TLB to the data store for a first process being swapped out of the processor and to selectively copy data from the data store to the TLB for a second process being swapped into to the processor.
    Type: Application
    Filed: September 16, 2005
    Publication date: March 22, 2007
    Inventors: James Callister, Eric Delano, Rohit Bhatia, Shawn Walker, Mark Gibson
  • Publication number: 20060080746
    Abstract: Methods for the efficient production of cloned porcine fetuses/piglets following the production of cloned embryos, including culture of the embryos for extended periods prior to transfer of the embryos into the uterus of the recipient. Transfer can be accomplished surgically or through less-invasive laparoscopic or non-surgical transfer.
    Type: Application
    Filed: September 28, 2005
    Publication date: April 13, 2006
    Applicant: ViaGen, Inc.
    Inventors: Scott Davis, Shawn Walker, Irina Polejaeva
  • Publication number: 20060004962
    Abstract: A cache memory system capable of adaptively accommodating various memory line sizes comprises cache memory and cache logic. The cache memory has sets of ways. The cache logic is configured to request a memory line in response to a cache miss, and the memory line represents a portion of a way line. The cache logic is configured to select one of the ways based on which portion of the way line is represented by the memory line. The cache logic is further configured to store the memory line in the selected way.
    Type: Application
    Filed: July 2, 2004
    Publication date: January 5, 2006
    Inventors: Shawn Walker, Donald Soltis, Karl Brummel