Abstract: Methods and systems for a fast drop recovery for a TCP connection are disclosed. Aspects of one method may include a receiving device on a network receiving an out-of-order data. The receiving device may then signal to a transmitting device on the network, which sent the out-of-order packet, to enter a congestion alleviation mode without waiting for a delay period. The network packet transfer may be via TCP protocol, for example. The delay period may comprise a retransmission time-out period if the receiving device does not save isles. If the receiving device does save one or more isles, the delay period may be a period associated with delayed ACK. The signal may comprise a TCP option and/or an available TCP flag. The signal may also comprise, for example, three duplicate ACKs. Other similar signals may be used for networks that use other protocols than TCP.

Abstract: A method for processing a datagram, including receiving an initial fragment of the datagram over a communication link and classifying in an initial classification the initial fragment as a first fragment, a middle fragment, or a last fragment of the datagram. The method further includes receiving one or more subsequent fragments over the communication link, following the initial fragment, and classifying each of the one or more subsequent fragments in respective subsequent classifications so as to find among the subsequent fragments at least one of the first fragment, the middle fragment, and the last fragment of the datagram. Responsive to the initial and the one or more subsequent classifications, a determination is made whether the datagram is completely constituted by the initial fragment and no more than two of the subsequent fragments. The datagram is reassembled responsive to the determination.

Abstract: Methods and systems for supplying power to multiple voltage islands using a single supply source are disclosed. Aspects of one method may include providing power to a first of a plurality of voltage islands, and individually controlling providing of power to each of a remaining portion of the plurality of voltage islands. For example, when an electronic system is first powered on, a low current voltage source may be used to supply power to a primary voltage island. As a higher current voltage source becomes available, power derived from the higher current voltage source may be provided to the primary voltage island and to secondary voltage islands. Power to each of the secondary voltage islands may be, for example, individually controlled via a power MOS transistor. The power MOS transistor may also be configured to allow a faster blocking time than unblocking time.

Abstract: A system may include multiple logic devices, a power input, and a logic controller. The power input may be configured to provide the auxiliary power to the logic devices. The logic controller may be configured to select a group of the logic devices for disabling the auxiliary power based, at least in part, on priority levels asserted by each of the logic devices, and disable the auxiliary power to the selected group of logic devices.

Abstract: Methods and systems for supplying power to multiple voltage islands using a single supply source are disclosed. Aspects of one method may include providing power to a first of a plurality of voltage islands, and individually controlling providing of power to each of a remaining portion of the plurality of voltage islands. For example, when an electronic system is first powered on, a low current voltage source may be used to supply power to a primary voltage island. As a higher current voltage source becomes available, power derived from the higher current voltage source may be provided to the primary voltage island and to secondary voltage islands. Power to each of the secondary voltage islands may be, for example, individually controlled via a power MOS transistor. The power MOS transistor may also be configured to allow a faster blocking time than unblocking time.

Abstract: Various example implementations are disclosed. According to one example implementation, a system may include multiple logic devices, a power input, and a logic controller. The logic devices may each be configured to assert a request for auxiliary power to a logic controller. The power input may be configured to provide the auxiliary power to one or more of the logic devices. The logic controller may be configured to poll the logic devices by polling less than all of the logic devices at a time to determine whether the logic devices assert the request for the auxiliary power.

Abstract: A network interface device includes a bus interface that communicates over a bus with a host processor and memory, and a network interface that sends and receive data packets carrying data over a packet network. A protocol processor conveys the data between the network interface and the memory via the bus interface while performing protocol offload processing on the data packets in accordance with multiple different application flows. The bus interface queues the data for transmission over the bus in a plurality of queues that are respectively assigned to the different application flows, and transmits the data over the bus according to the queues.

Abstract: A method for communication is disclosed and may include, in a network interface device, parsing a portion of a TCP segment into one or more portions of Internet Small Computer Systems Interface (iSCSI) Protocol Data Units (PDUs). A header and/or a payload for one or more of the parsed iSCSI PDUs may be recovered. Concurrent with parsing of a remaining portion of the TCP segment to recover a remaining portion of PDUs, the recovered header may be evaluated and/or the recovered payload may be routed external to the network interface device for processing. The evaluating and the routing may occur independently of the parsing within the network interface device. Respective separate physical processors may be used for the parsing and the recovering. The respective separate processors for recovering may be used for the evaluating and the routing.

Abstract: Certain aspects of a method and system for transparent transmission control protocol (TCP) offload with transmit and receive coupling are disclosed. Aspects of a method may include collecting at least one received TCP segment for a determined network flow via a network interface card (NIC) processor. The state information for the received TCP segment and state information for transmitted TCP segments for the determined network flow may be stored at the NIC without transferring state information for the received TCP segment and the state information for the transmitted TCP segments to a host system communicatively coupled to the NIC. A new TCP segment comprising the collected TCP segments may be generated after a termination event occurs. The generated new TCP segment, new state information for the generated new TCP segment, and the state information for the transmitted TCP segments may be communicated to the host system for TCP offload.

Abstract: A method includes accepting a simulation task for simulation by a simulator that controls multiple co-simulators. Each of the multiple co-simulators is assigned to execute one or more respective sub-tasks of the simulation task. The simulation task is executed by invoking each co-simulator to execute the respective assigned sub-tasks.

Abstract: Certain aspects of a method and system for configuring a plurality of network interfaces that share a physical interface (PHY) may include a system comprising one or more physical network interface controllers (NICs) and two or more virtual NICs. One or more drivers associated with each of the virtual NICs that share one or more Ethernet ports associated with the physical NICs may be synchronized based on controlling one or more parameters associated with one or more Ethernet ports. One or more wake on LAN (WoL) patterns associated with each of the drivers may be detected at one or more Ethernet ports. A wake up signal may be communicated to one or more drivers associated with the detected WoL patterns. One of the drivers may be appointed to be a port master driver. If a failure of the appointed port master driver is detected, another driver may be appointed to be the port master driver.

Abstract: A method for a receiver to perform processing of incoming data segments transmitted over a network by a transmitter in accordance with a transport protocol. The segments incorporate sequence values indicative of a transmission order of the segments. The method consists of receiving the data segments over the network in a reception order. Then, for each segment received in the reception order, the sequence values of the received segment and of the segments received earlier in the reception order are compared in order to assign the received segment a classification identity as an in-order or out-of-order segment. The method further includes writing the segments, in a writing order that is substantially identical to the reception order, to respective locations in an output buffer responsive to the classification identity of each segment, so that the segments in the output buffer are arranged in the transmission order.

Abstract: Certain aspects of a method and system for processing status blocks based on interrupt mapping may be disclosed. Exemplary aspects of the method may include determining whether a particular status block has been processed by at least one CPU based on comparing a value of a first register with a value of a second register, wherein the first register may comprise a running index value of at least one client segment within the particular status block and the second register may comprise a current running index value of at least one client segment. An interrupt may be generated, if the value of the first register is not equal to the value of the second register. The particular status block may be processed by at least one CPU based on the generated interrupt.

Abstract: Certain aspects of a method and system for configuring a plurality of network interfaces that share a physical interface (PHY) may include a system comprising one or more physical network interface controllers (NICs) and two or more virtual NICs. One or more drivers associated with each of the virtual NICs that share one or more Ethernet ports associated with the physical NICs may be synchronized based on controlling one or more parameters associated with one or more Ethernet ports. One or more wake on LAN (WoL) patterns associated with each of the drivers may be detected at one or more Ethernet ports. A wake up signal may be communicated to one or more drivers associated with the detected WoL patterns. One of the drivers may be appointed to be a port master driver. If a failure of the appointed port master driver is detected, another driver may be appointed to be the port master driver.

Abstract: A computing method includes accepting a definition of a computing task (68), which includes multiple atomic Processing Elements (PEs—76) having execution dependencies (80). Each execution dependency specifies that a respective first PE is to be executed before a respective second PE. The computing task is compiled for concurrent execution on a multiprocessor device (32), which includes multiple processors (44) that are capable of executing a first number of the PEs simultaneously, by arranging the PEs, without violating the execution dependencies, in an invocation data structure (90) including a second number of execution sequences (98) that is greater than one but does not exceed the first number. The multiprocessor device is invoked to run software code that executes the execution sequences in parallel responsively to the invocation data structure, so as to produce a result of the computing task.

Abstract: A network interface device includes a bus interface that communicates over a bus with a host processor and memory, and a network interface that sends and receive data packets carrying data over a packet network. A protocol processor conveys the data between the network interface and the memory via the bus interface while performing protocol offload processing on the data packets in accordance with multiple different application flows. The bus interface queues the data for transmission over the bus in a plurality of queues that are respectively assigned to the different application flows, and transmits the data over the bus according to the queues.

Abstract: A network interface device includes a bus interface that communicates over a bus with a host processor and memory, and a network interface, including at least first and second physical ports, which are coupled to send and receive data packets carrying data over a packet network. A protocol processor includes a single transmit processing pipeline and a single receive processing pipeline, which are coupled between the bus interface and the network interface so as to convey the data between both of the first and second physical ports of the network interface and the memory via the bus interface while performing protocol offload processing on the data packets.

Abstract: A network interface device includes a bus interface that communicates over a bus with a host processor and memory, and a network interface that sends and receive data packets carrying data over a packet network. A protocol processor conveys the data between the network interface and the memory via the bus interface while performing protocol offload processing on the data packets in accordance with multiple different application flows. The bus interface queues the data for transmission over the bus in a plurality of queues that are respectively assigned to the different application flows, and transmits the data over the bus according to the queues.

Abstract: A method for design simulation includes partitioning a verification task of a design (100) into a first plurality of atomic Processing Elements (PEs-108) having execution dependencies (112), each execution dependency specifying that a respective first PE is to be executed before a respective second PE. The method further includes computing an order for executing the PEs on a multiprocessor device (32), which includes a second plurality of processors (44) operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy. The order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies, irrespective of the scheduling policy. The PEs are executed on the processors in accordance with the computed order and the scheduling policy, to produce a simulation result. A performance of the design is verified responsively to the simulation result.

Abstract: A method for communication is disclosed and may include, in a network interface device, parsing a portion of a TCP segment into one or more portions of Internet Small Computer Systems Interface (iSCSI) Protocol Data Units (PDUs). A header and/or a payload for one or more of the parsed iSCSI PDUs may be recovered. Concurrent with parsing of a remaining portion of the TCP segment to recover a remaining portion of PDUs, the recovered header may be evaluated and/or the recovered payload may be routed external to the network interface device for processing. The evaluating and the routing may occur independently of the parsing within the network interface device. Respective separate physical processors may be used for the parsing and the recovering. The respective separate processors for recovering may be used for the evaluating and the routing.