Abstract: A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.

Abstract: A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.

Abstract: A mechanism is provided for simultaneous photolithographic mask and target optimization (SMATO). A lithographic simulator generates an image of a mask shape on a wafer thereby forming one or more lithographic contours. A mask and target movement module analytically evaluates a direction for mask and target movement thereby forming a plurality of pairs of mask and target movements. The mask and target movement module identifies a best pair of mask and target movements from the plurality of mask and target movements that minimizes a weighted cost function. A shape adjustment module adjusts at least one of a target shape or the mask shape based on the best pair of mask and target movements.

Abstract: A mechanism is provided for simultaneous optical proximity correction (OPC) and decomposition for double exposure lithography. The mechanism begins with two masks that are equal to each other and to the target. The mechanism simultaneously optimizes both masks to obtain a wafer image that both matches the target and is robust to process variations. The mechanism develops a lithographic cost function that optimizes for contour fidelity as well as robustness to variation. The mechanism minimizes the cost function using gradient descent. The gradient descent works on analytically evaluating the derivative of the cost function with respect to mask movement for both masks. It then moves the masks by a fraction of the derivative.

Abstract: A contour of a mask design for an integrated circuit is modified to compensate for systematic variations arising from non-optical effects such as stress, well proximity, rapid thermal anneal, or spacer thickness. Electrical characteristics of a simulated integrated circuit chip fabricated using the mask design are extracted and compared to design specifications, and one or more edges of the contour are adjusted to reduce the systematic variation until the electrical characteristic is within specification. The particular electrical characteristic preferably depends on which layer is to be fabricated from the mask: on-current for a polysilicon; resistance for contact; resistance and capacitance for metal; current for active; and resistance for vias. For systematic threshold voltage variation, the contour is adjusted to match a gate length which corresponds to an on-current value according to pre-calculated curves for contour current and gate length at a nominal threshold voltage of the chip.

Abstract: A mechanism is provided for harmonic mean optical proximity correction (HMOPC). A lithographic simulator in a HMOPC mechanism generates an image of a mask shape based on a target shape on a wafer thereby forming one or more lithographic contours. A cost function evaluator module determines a geometric cost function associated with the one or more lithographic contours. An edge movement module minimizes the geometric cost function thereby forming a minimized geometric cost function. The edge movement module determines a set of edge movements for each slice in a set of slices associated with the one or more lithographic contours using the minimized geometric cost function. The edge movement module moves the edges of the mask shape using the set of edge movements for each slice in the set of slices. The HMOPC mechanism then produces a clean mask shape using the set of edge movements.

Abstract: An approach is provided that computes electrical delay ranges that correspond to a number of shapes included in a hardware design layout. The electrical delay ranges are converted to shape tolerances for each of the shapes. A lithography mask of the hardware design layout is generated using the shape tolerances so that the images of the shapes in the mask produced lie within the shape tolerances that correspond to the respective shape.

Abstract: A mechanism is provided for simultaneous photolithographic mask and target optimization (SMATO). A lithographic simulator generates an image of a mask shape on a wafer thereby forming one or more lithographic contours. A mask and target movement module analytically evaluates a direction for mask and target movement thereby forming a plurality of pairs of mask and target movements. The mask and target movement module identifies a best pair of mask and target movements from the plurality of mask and target movements that minimizes a weighted cost function. A shape adjustment module adjusts at least one of a target shape or the mask shape based on the best pair of mask and target movements.

Abstract: An approach that provides electrically driven optical proximity correction is described. In one embodiment, there is a method for performing an electrically driven optical proximity correction. In this embodiment, an integrated circuit mask layout representative of a plurality of layered shapes each defined by features and edges is received. A lithography simulation is run on the mask layout. An electrical characteristic is extracted from the output of the lithography simulation for each layer of the mask layout. A determination as to whether the extracted electrical characteristic is in conformance with a target electrical characteristic is made. Edges of the plurality of layered shapes in the mask layout are adjusted in response to determining that the extracted electrical characteristic for a layer in the mask layout fails to conform with the target electrical characteristic.

Abstract: Mechanism are provided for model-based retargeting of photolithographic layouts. An optical proximity correction is performed on a set of target patterns for a predetermined number of iterations until a counter value exceeds a maximum predetermined number of iterations in order to produce a set of optical proximity correction mask shapes. A set of lithographic contours is generated for each of the set of optical proximity correction mask shapes in response to the counter value exceeding the maximum predetermined number of iterations. A normalized image log slope (NILS) extraction is performed on the set of target shapes and use the set of lithographic contours to produce NILS values. The set of target patterns is modified based on the NILS values in response to the NILS values failing to be within a predetermined limit. The steps are repeated until the NILS values are within the predetermined limit.

Abstract: A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.

Abstract: A contour of a mask design for an integrated circuit is modified to compensate for systematic variations arising from non-optical effects such as stress, well proximity, rapid thermal anneal, or spacer thickness. Electrical characteristics of a simulated integrated circuit chip fabricated using the mask design are extracted and compared to design specifications, and one or more edges of the contour are adjusted to reduce the systematic variation until the electrical characteristic is within specification. The particular electrical characteristic preferably depends on which layer is to be fabricated from the mask: on-current for a polysilicon; resistance for contact; resistance and capacitance for metal; current for active; and resistance for vias. For systematic threshold voltage variation, the contour is adjusted to match a gate length which corresponds to an on-current value according to pre-calculated curves for contour current and gate length at a nominal threshold voltage of the chip.

Abstract: An approach that provides electrically driven optical proximity correction is described. In one embodiment, there is a method for performing an electrically driven optical proximity correction. In this embodiment, an integrated circuit mask layout representative of a plurality of layered shapes each defined by features and edges is received. A lithography simulation is run on the mask layout. An electrical characteristic is extracted from the output of the lithography simulation for each layer of the mask layout. A determination as to whether the extracted electrical characteristic is in conformance with a target electrical characteristic is made. Edges of the plurality of layered shapes in the mask layout are adjusted in response to determining that the extracted electrical characteristic for a layer in the mask layout fails to conform with the target electrical characteristic.