Patents by Inventor Shayan S. Garani

Shayan S. Garani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9214963
    Abstract: A data storage system configured to adaptively code data and related methods are disclosed. In some embodiments of the present invention, a data storage system includes a controller and a non-volatile memory array having a plurality of memory pages. The controller includes a channel monitor that determines the quality of read signals from the pages when they are read, and provides adjustment metrics to aid in the selection of a code rate, such as a code rate for a low-density parity-check (LDPC) code. In this way, the code rate used for data encoding can be dynamically adjusted to accommodate degradation of the non-volatile memory array over its useable life.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: December 15, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shayan S. Garani, Kent D. Anderson, Anantha Raman Krishnan, Guangming Lu, Shafa Dahandeh, Andrew J. Tomlin
  • Patent number: 9203434
    Abstract: Some embodiments of the invention are directed to systems and methods for an optimized and efficient encoding scheme that can accommodate higher block lengths of data. Some embodiments generally relate to: (1) coding structures for a new class of LDPC matrices based on algebraic relations, and (2) encoding method that achieves the R=1?k/n exact bound on code rate. In addition, in some embodiments, the coding structures efficiently create matrices with excellent error-correcting properties and are devoid of short cycles (leading to robust performance). The implementations of the coding structures are scalable over a range of code rates and block lengths.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: December 1, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventor: Shayan S. Garani
  • Patent number: 8990668
    Abstract: Embodiments of decoding data stored in solid-state memory arrays are disclosed. In one embodiment, multiple read operations are performed while taking inter-cell interference (ICI) into account. Soft-decision information, such as log-likelihood ratios (LLRs), is determined by using known data and its corresponding multi-read output. Soft-decision information is provided to a detector. Reliability is improved and performance is increased.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 24, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventors: Anantha Raman Krishnan, Shayan S. Garani, Kent D. Anderson
  • Patent number: 8856615
    Abstract: A data storage device is disclosed comprising a non-volatile memory (NVM). First data is written to a first area of the NVM, and a first estimated data sequence is read from the first area of the NVM. The first estimated data sequence is first decoded, and a log-likelihood ratio (LLR) is first updated based on the first decode. Second data is written to a second area of the NVM, and a second estimated data sequence is read from the second area of the non-volatile memory. The second estimated data sequence is second decoded in response to the first updated LLR, and the LLR is second updated based on the second decode.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: October 7, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventors: Anantha Raman Krishnan, Shayan S. Garani, Kent D. Anderson, Shafa Dahandeh
  • Patent number: 8760782
    Abstract: A disk drive is configured to decode data written over a plurality of data tracks using joint self-iterating soft equalization and an iterative turbo 2-D MAP-based detection, by performing soft self-iterating linear 2-D MMSE equalization on received input samples; computing MMSE estimates for coefficients of a 2-D equalization filter based on a-priori values, mean of the a-priori values, the 2-D filter and the received input samples; updating the coefficients of the 2-D filter using a variance based on the a-priori values when carrying out a first iteration and based on an extrinsic LLR when carrying out subsequent iterations; determining values of the individual bits in the input samples using the updated coefficients; computing an output LLR of each individual received sample based on the computed MMSE estimate, the mean and the variance, and computing the extrinsic LLR by subtracting a priori LLR from the output LLR.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: June 24, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shayan S. Garani, Yiming Chen
  • Patent number: 8582223
    Abstract: Decoding data written over a plurality of tracks includes selecting a mask that accounts for Inter-Symbol-Interference, the mask including channel coefficients and defining a trellis defining a plurality of states; receiving a signal corresponding to an input pixel from each of the plurality of tracks and generating equalized samples therefrom; computing transition branch probabilities for each input vector based on a Gaussian noise distribution using the equalized samples, ideal samples and a priori probabilities of the input vector; computing forward and backward probabilities via recursions using the computed transition branch probabilities; combining the forward, backward and transition branch probabilities to generate a-posteriori probabilities for the input vector; marginalizing the a-posteriori probabilities over values of neighboring pixels to generate an a-posteriori probability for a pixel of the input vector in a given state, and decoding the pixel as a first or second logical state from the margin
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: November 12, 2013
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shayan S. Garani, Yiming Chen
  • Patent number: 8290102
    Abstract: A method is provided. The method comprises calibrating noise prediction parameters by adapting one or more biases, adapting one or more filter coefficients using the adapted one or more biases, and adapting one or more prediction error variances using the adapted one or more biases and the adapted one or more filter coefficients.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: October 16, 2012
    Assignees: STMicroelectronics, Inc., STMicroelectronics SRL
    Inventors: Mustafa Kaynak, Sivagnanam Parthasarathy, Stefano Valle, Shayan S. Garani
  • Publication number: 20110085628
    Abstract: A method is provided. The method comprises calibrating noise prediction parameters by adapting one or more biases, adapting one or more filter coefficients using the adapted one or more biases, and adapting one or more prediction error variances using the adapted one or more biases and the adapted one or more filter coefficients.
    Type: Application
    Filed: January 14, 2010
    Publication date: April 14, 2011
    Applicants: STMicroelectronics, Inc., STMicroelectronics Srl.
    Inventors: Mustafa N. Kaynak, Sivagnanam Parthasarathy, Stefano Valle, Shayan S. Garani
  • Publication number: 20100169736
    Abstract: A system and method is capable of performing a Low Density Parity Check (LDPC) coding operation on-the-fly without using a generator matrix. The system and method includes an input configured to receive data and an output configured to output a plurality of codewords. The system and method also includes a processor coupled between the input and the output. The processor is configured to encode the received data and produce the plurality of codewords using a plurality of parity bits. The processor creates the plurality of parity bits on-the-fly using a portion of an LDPC matrix and a protograph matrix.
    Type: Application
    Filed: October 2, 2009
    Publication date: July 1, 2010
    Applicant: STMicroelectronics, Inc.
    Inventor: Shayan S. Garani