Abstract: A process is described for forming a plasma nitride (SiNy) layer and a tapered opening through the layer so that the opening may more readily receive ohmic contacts. During the formation of the plasma nitride layer, more silane (over ammonia) is used to form a silicon rich upper portion of the layer. During the subsequent etching of this layer to form the opening, the silicon rich portion of the plasma nitride layer etches more quickly than the remainder of the layer and this results in the formation of the tapered opening through the layer.

Abstract: A process for forming self-aligned, metal plated substrate regions and polysilicon members is described. Oxide lips or borders are formed along the sides of the polysilicon members beneath a masking member. An oxide damaging ion bombardment is used to damage the oxide on the substrate, however, the oxide lips remain protected because of the overlying masking member. A controlled etch is used to remove the damaged oxide leaving the polysilicon member separated from adjacent regions by the oxide lips. A tungsten deposition is used to form metal plating over the exposed substrate regions and over the polysilicon member, however, no metal is formed over the oxide lips.

Abstract: A process for forming an electrical contact region between layers of polysilicon with an integral polysilicon resistor during the fabrication of MOS integrated circuits is disclosed. The contact region which does not require critical alignments, may be formed directly over an active channel or buried (substrate) contact. A silicon nitride mask is formed at the location of the contact region on the first polysilicon layer thereby allowing a thick oxide to be grown on the remainder of the substrate. After removal of the silicon nitride mask, a second polysilicon layer is formed which contacts the first layer at the contact region and defines the resistor. A doping step is used to establish the resistance of the resistor. The process permits the fabrication, by way of example, of a static (bistable) MOS memory cell employing polysilicon loads with an area of approximately 1.5 mils.sup.2.