Abstract: An advanced output buffer circuit is described which has a reduced voltage swing, in order to increase the buffer speed and to reduce electrical noise due to lower instant current flow. The reduced voltage swing is at the buffer circuit output terminal, acting in response to control signals and a data signal on its input terminals. A first inverter stage has as its input the input terminal at which is applied the data signal, and delays the data signal. A second inverter stage with its input being the input terminal at which is applied the data signal, provides an inverted data signal at its output. A blocking circuit, responsive to the control signals, blocks the data signal and the inverted data signal. A biasing circuit, also responsive to the control signals, biases a first and second output node to a first intermediate voltage level, the first and second output nodes being connected to outputs of the blocking circuit.