Patents by Inventor Shefali Walia

Shefali Walia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Duty cycle adjustment circuit with independent range and step size control
    Patent number: 11569806
    Abstract: Duty cycle adjustment circuitry includes a first stage, a second stage, and decoder circuitry. The first stage includes a first strength tuning circuit having first inverter branches, and a first fine tuning circuit having second inverter branches. The first strength tuning circuit and the first fine tuning circuit are coupled in parallel. The second stage includes a second strength tuning circuit having third inverter branches, and a second fine tuning circuit having fourth inverter branches. The second strength tuning circuit and the second fine tuning circuit are coupled in parallel. Further, the second stage is electrically coupled to the first stage. The decoder circuitry is electrically coupled to the first stage and the second stage. The decoder circuitry controls the first strength tuning circuit independently from the first fine tuning circuit to adjust the duty cycle of an input signal received by the duty cycle adjustment circuitry.
    Type: Grant
    Filed: February 2, 2022
    Date of Patent: January 31, 2023
    Assignee: Synopsys, Inc.
    Inventors: Kuan Zhou, David Da-Wei Lin, Vladimir Zlatkovic, Shefali Walia, Youssef Mamdouh El-Toukhy, Abdelrahman Alaa Gouda, Alexander A. Alexeyev
  • DUTY CYCLE ADJUSTMENT CIRCUIT WITH INDEPENDENT RANGE AND STEP SIZE CONTROL
    Publication number: 20220247398
    Abstract: Duty cycle adjustment circuitry includes a first stage, a second stage, and decoder circuitry. The first stage includes a first strength tuning circuit having first inverter branches, and a first fine tuning circuit having second inverter branches. The first strength tuning circuit and the first fine tuning circuit are coupled in parallel. The second stage includes a second strength tuning circuit having third inverter branches, and a second fine tuning circuit having fourth inverter branches. The second strength tuning circuit and the second fine tuning circuit are coupled in parallel. Further, the second stage is electrically coupled to the first stage. The decoder circuitry is electrically coupled to the first stage and the second stage. The decoder circuitry controls the first strength tuning circuit independently from the first fine tuning circuit to adjust the duty cycle of an input signal received by the duty cycle adjustment circuitry.
    Type: Application
    Filed: February 2, 2022
    Publication date: August 4, 2022
    Inventors: Kuan ZHOU, David Da-Wei LIN, Vladimir ZLATKOVIC, Shefali WALIA, Youssef Mamdouh EL-TOUKHY, Abdelrahman Alaa GOUDA, Alexander A. ALEXEYEV
  • Method and apparatus for using DFE in a system with non-continuous data
    Patent number: 8553754
    Abstract: A decision feedback equalization (DFE) receiver and method are provided. The DFE receiver is configured to sample data bits from a data bus. The DFE receiver includes a data sampler configured to sample a current data bit from the data bus using one of a first, second and third voltage reference. The DFE receiver also includes multiplexing logic configured to select one of the first, second and third voltage references based on a prior data bus level. The wherein the first voltage reference is selected if the prior data bus level was a logic zero. The second voltage reference is selected if the prior data bus level was a logic one. The third voltage reference is selected if the prior data bus level was tri-state.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: October 8, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ramon Mangaser, Shefali Walia, Edoardo Prete, Jonathan P. Dowling, Gerald R. Talbot, Sharad N. Vittal
  • METHOD AND APPARATUS FOR USING DFE IN A SYSTEM WITH NON-CONTINUOUS DATA
    Publication number: 20120155529
    Abstract: A decision feedback equalization (DFE) receiver and method are provided. The DFE receiver is configured to sample data bits from a data bus. The DFE receiver includes a data sampler configured to sample a current data bit from the data bus using one of a first, second and third voltage reference. The DFE receiver also includes multiplexing logic configured to select one of the first, second and third voltage references based on a prior data bus level. The wherein the first voltage reference is selected if the prior data bus level was a logic zero. The second voltage reference is selected if the prior data bus level was a logic one. The third voltage reference is selected if the prior data bus level was tri-state.
    Type: Application
    Filed: December 20, 2010
    Publication date: June 21, 2012
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Ramon Mangaser, Shefali Walia, Edoardo Prete, Jonathan P. Dowling, Gerald R. Talbot, Sharad N. Vittal