Abstract: A direct memory access system consists of a direct memory access controller establishing a direct memory access data channel and including a first interface for coupling to a memory. A second interface is for coupling to a plurality of nodes. And a processor is coupled to the direct memory access controller and coupled to the second interface, wherein the processor configures the direct memory access data channel to transfer data between a programmably selectable respective one or more of the plurality of nodes and the memory. In some embodiments, the plurality of nodes are a digital signal processor memory and a host processor memory of a multi-media processor platform to be implemented in a wireless multi-media handheld telephone.

Abstract: A wireless communications architecture having first and second synchronous memory devices coupled to a virtual channel memory controller by corresponding first and second data buses, and a shared address and control bus interconnecting the virtual channel memory controller and the first and second synchronous memory devices. The first and second synchronous memory devices are addressed with the shared address bus, and the first and second memory locations are accessed via the first and second data buses, respectively.

Abstract: A direct memory access system consists of a direct memory access controller establishing a direct memory access data channel and including a first interface for coupling to a memory. A second interface is for coupling to a plurality of nodes. And a processor is coupled to the direct memory access controller and coupled to the second interface, wherein the processor configures the direct memory access data channel to transfer data between a programmably selectable respective one or more of the plurality of nodes and the memory. In some embodiments, the plurality of nodes are a digital signal processor memory and a host processor memory of a multi-media processor platform to be implemented in a wireless multi-media handheld telephone.

Abstract: A wireless communications architecture having first and second synchronous memory devices coupled to a virtual channel memory controller by corresponding first and second data buses, and a shared address and control bus interconnecting the virtual channel memory controller and the first and second synchronous memory devices. The first and second synchronous memory devices are addressed with the shared address bus, and the first and second memory locations are accessed via the first and second data buses, respectively.

Abstract: A wireless communications architecture having first and second synchronous memory devices coupled to a virtual channel memory controller by corresponding first and second data buses, and a shared address and control bus interconnecting the virtual channel memory controller and the first and second synchronous memory devices. The first and second synchronous memory devices are addressed with the shared address bus, and the first and second memory locations are accessed via the first and second data buses, respectively.

Abstract: A digital receiver (200) and transmitter (300), wherein the digital receiver includes a plurality of antennas (202) for receiving uplink radio frequency signals; a plurality of analog to digital converters (210) for converting the received radio frequency signals into digital signals; a switched digital down converter (214) for down converting one of the digital signals to a baseband IF signal; and a channel processor (228) for recovering one of a plurality of communication channels contained within the baseband IF signal.

Abstract: An infrared channel includes an IR transmitter circuit (302) and an IR receiver circuit (304). The transmitter circuit encodes data packets (400) which include a precursor segment, a synchronization segment, and a data field, the data field including data words, which words are bytes of data encoded by adding ones complement data bits and interleaving data subfields. The data fields are for infrared emission by the light source. A receiver circuit processor (316 or 508) is coupled to input samples to detect the presence of a precursor during a predetermined time period, and sleeping for a time interval, between inputting samples, which is substantially longer than the predetermined time period. The transmitter circuit transmits the precursor for a period of time at least as long as the sleep interval.

Abstract: A display system includes a display panel (200) having a full display screen area (303) upon which images can be generated for viewing. An image control circuit (400, 501) controls the operation of the display panel such that only a partial display field, or area, (305) is controlled to generate images in a first operating mode to conserve power and the full display screen area is controlled to generate images in a second operating mode.

Abstract: Generally stated, an apparatus and method for routing a digitized radio frequency (RF) signal 140-143 to a plurality of paths is described herein. In accordance with a first preferred embodiment, the apparatus comprises a digital upconverter/modulator (DUC) 125, 129 coupled to a scaling and switching network 100N which is comprised of, at minimum, a first, second, third and fourth digital switch, and a first, second and third adder. Within the scaling and switching network 100N, the first digital switch is responsive to the DUC 125,129. The first adder is responsive to the first and second digital switches, while the second adder is responsive to the third and fourth digital switches. Finally, the third adder is responsive to the first and second adders.